This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

A system is disclosed. The system may include a processor and a memory connected to the processor. A first storage device may be connected to the processor. The first storage device may include a first storage portion, which may include a memory page. The first storage portion may extend the memory. A second storage device may also be connected to the processor. The second storage device may also include a second storage portion. The second storage portion may also extend the memory. A load balancing daemon may migrate the memory page from the first storage portion of the first storage device to the second storage portion of the second storage device based at least in part on a first update count of the first storage device and a second update count of the second storage device.

A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.

A data storage apparatus includes a storage device; a controller to control data input and output operations of the storage device; and a swap memory provided in an outside of the controller, wherein the controller includes a thread manager to perform a preparation operation on a first thread included in a task in response to a request for processing the task, request the storage device to process the first thread on which the preparation operation has been performed, perform a preparation operation on at least one subsequent thread following the first thread while the storage device processes the first thread, and store context data of the first thread and the at least one subsequent thread in the swap memory, wherein the task includes the first thread and the at least one subsequent thread, and the preparation operation includes an address mapping operation.

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.

A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.