Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

A processing device in a memory sub-system identifies a first memory device and a second memory device and configures the second memory device with a zone namespace. The processing device identifies a first portion and a second portion of the first memory device, the first portion storing zone namespace metadata corresponding to the zone namespace on the second memory device. The processing device further exposes the second portion of the first memory device to a host system as a non-zoned addressable memory region.

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.

During execution of garbage collection, an application receives a first request to overwrite a reference field of an object, the object comprising a first reference and the first request comprising a memory address at which the reference field is stored, and a second reference to be written to the reference field. Responsive to receiving the first request, the system determines a current remembered set phase, and loads the first reference. The application determines that remembered set metadata of the first reference does not match the current remembered set phase. Responsive to that determination, the application adds an entry to a remembered set data structure, modifies the second reference to include the current remembered set phase as the remembered set metadata, and stores the modified second reference to the reference field. In subsequent writes to the reference field, the application refrains from adding to the remembered set data structure.

A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

A system and method for lifecycle-aware persistent key-value storage. In some embodiments, the method includes: receiving a first modification instruction, for a first key; incrementing a device write counter for a persistent storage device; selecting a first block, from the persistent storage device, for the first key, based on a current value of the device write counter; and storing the first key and an associated first value in the first block.

Methods, systems, and devices for cache management in a memory subsystem are described. A device may determine to perform an eviction procedure for a bank of a volatile memory that operates as a cache for a non-volatile memory. The eviction procedure may save data from the bank of the volatile memory to the non-volatile memory. The device may determine an activity status for at least one buffer in a pool of buffers that are coupled with the volatile memory and the non-volatile memory. The device may select the at least one buffer in the pool of buffers for the eviction procedure for the bank of the volatile memory based at least in part on the activity status for that buffer.

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.

A method for managing a memory apparatus including a plurality of non-volatile (NV) memory elements includes: programming a physical block of a specific NV memory element, including: receiving a host command from a host; obtaining a host address and data from the host command; and linking the host address to a page of a physical block of the specific NV memory element and storing the data into the physical block. Before the pages of the physical block are fully programmed, a temporary local page linking address table is stored and is updated each time a linking relationship is changed. When the memory apparatus is to be shut down, the temporary local page linking address table is written to the specific NV memory element; and when the memory apparatus begins a start-up process, a global page address linking table is built by reading the local page address linking table.

Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.