A method for page management in a memory system may include allocating a page of a mirror memory, copying a valid page from a block of device memory at a device to the page of the mirror memory, remapping the valid page from the block of device memory to the mirror memory, and modifying the block of device memory. The method may further include copying the valid page from the mirror memory to a free page at the device, and remapping the valid page from the mirror memory to the free page at the device. The remapping may be performed using a memory coherent interface. The method may further include deallocating a portion of the mirror memory associated with the valid page based on copying the valid page from the mirror memory.

An operating method of a memory controller configured to control a memory device including memory blocks each for storing a plurality of pages is provided. The operating method includes transferring a program command to the memory device based on a write request from a host, updating a valid page bitmap representing validity of a plurality of pages based on valid page information received from the memory device, calculating a fragmentation ratio representing a segmentation degree between at least one valid page and at least one invalid page of a memory block based on the valid page bitmap, determining source blocks among the memory blocks in ascending order of fragmentation ratios, and performing garbage collection on the source blocks.

A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

According to one embodiment, there is provided a memory system including a non-volatile memory and a controller. The non-volatile memory includes a plurality of physical blocks. The controller is connected to any of the plurality of physical blocks via a plurality of channels. The controller is configured to construct a plurality of logical blocks and, read or write data from or into any of the plurality of logical blocks constructed. The logical blocks are management units in which any of the physical blocks is grouped across the plurality of channels. The controller is configured to construct the plurality of logical blocks so that a first number of defective blocks and a second number of pseudo defective blocks for shortfall defective blocks with respect to a target number of defective blocks are distributed into the plurality of logical blocks.

A storage device includes a controller and nonvolatile memories. The controller receives write commands having virtual stream identifiers (IDs), receives discard commands having the virtual stream IDs, and determines a lifetime of write data to which each of the virtual stream IDs is assigned. The nonvolatile memories are accessed by the controller depending on physical stream IDs. The controller maps the virtual stream IDs and the physical stream IDs based on the lifetime of the write data.

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

A scheme for handling program errors is provided for a memory system which includes a memory device and a controller including firmware and a memory interface. The firmware issues commands for program operations to the memory interface. After detecting a failed program operation in a particular memory block, the firmware reroutes that program operation to a different location in a different memory block and takes further action to reduce the likelihood of a subsequent error occurring in the same memory block in which the failed program operation occurred.