G06F2212/7211

ADJUSTABLE MEMORY OPERATION SETTINGS BASED ON MEMORY SUB-SYSTEM OPERATING REQUIREMENTS
20230095179 · 2023-03-30 ·

A first set of memory access operations is performed at a memory sub-system based on first operation settings that are configured based on a first operating environment of a host system. A detection is made that the host system is operating in a second operating environment that is different from the first operating environment. A level of impact that each operating requirement of a set of operating requirements of the memory sub-system has on a performance of the memory sub-system in view of the second operating environment. A second set of memory access operations is determined based on a respective priority for each operating requirement of the set of operating requirements. A second set of memory access operations is performed at the memory sub-system based on the second set of memory access operation settings.

Parsing stream identifiers to determine data stream attributes

An example method of encoding data attributes by data stream identifiers includes: receiving, by a controller managing a memory device, a write command, wherein the write command specifies a first data item and an identifier of a data stream, wherein the data stream comprises the first data item and a second data item; determining, by parsing the identifier of the data stream, a data attribute encoded by the identifier of the data stream, wherein the data attribute is shared by the first data item and the second data item; determining, using the data attribute, a storage operation parameter; and transmitting, to the memory device, an instruction specifying the first data item and the storage operation parameter.

Technologies for media management in column-addressable memory media systems
11573735 · 2023-02-07 · ·

Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.

MEMORY SUB-SYSTEM FOR PERFORMING WEAR-LEVELING ADJUSTMENTS BASED ON MEMORY COMPONENT ENDURANCE ESTIMATIONS
20230031288 · 2023-02-02 ·

A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component. The processing device determines endurance values for the memory component. For each selected block of the plurality of blocks, the processing device determines an endurance estimation of the selected block based on at least one of a time to erase the selected block or an error statistic for the selected block, and updates an endurance value associated with the selected block based on the endurance estimation for the selected block. The processing device receives a write instruction to the memory component and distributes the write instruction to one or more of the blocks based on the endurance values. Other embodiments are described.

OPERATIONAL CODE STORAGE FOR AN ON-DIE MICROPROCESSOR

Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

STORAGE DEVICES, STORAGE CONTROLLERS, AND OPERATING METHODS OF STORAGE CONTROLLERS
20230036841 · 2023-02-02 ·

Provided are a storage device, a storage controller, and an operating method of the storage controller. The storage device according to the inventive concept includes a non-volatile memory and a storage controller. The non-volatile memory includes a plurality of memory blocks, each memory block includes physical units having different retention strengths due to process variations, and the retention strengths respectively correspond to times that physical units retain data before respective reclaim operations for the physical units. The storage controller receives a write request and data from a host, selects a first physical unit based on hotness of data and retention strengths, and controls the non-volatile memory to write data to the first physical unit.

Address mapping in memory systems
11487676 · 2022-11-01 · ·

A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.

Method and system for accelerating storage of data in write-intensive computer applications

A method of optimising a service rate of a buffer in a computer system having memory stores of first and second type is described. The method selectively services the buffer by routing data to each of the memory store of the first type and the second type based on read/write capacity of the memory store of the first type.

MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
20230037172 · 2023-02-02 ·

A memory system may include a memory controller and a memory device including a plurality of sequential areas. The memory controller may control the performance of a background media scan (BGMS) operation on one or more sequential areas among the plurality of sequential areas. The memory controller may receive an open command for allocating a buffer to a sequential area among the plurality of sequential areas, where first time information corresponds to a time at which the open command is received by the memory controller. The memory controller may calculate a first period based on the first time information, and determine, based on the first period, a skip area in which the BGMS operation is skipped among the plurality of sequential areas for each of a plurality of BGMS periods.

Media management operations based on health characteristics of memory cells

A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.