An average inter-pulse delay of a data unit of the memory device is calculated. An average temperature of the data unit is calculated. A first scaling factor based on the average inter-pulse delay and a second scaling factor based on the average temperature is obtained. A media management metric based on the first scaling factor and the second scaling factor is calculated. Responsive to determining that the media management metric satisfies a media management criterion, a media management operation on the data unit at a predetermined cycle count is performed.

A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component. The processing device determines endurance values for the memory component. For each selected block of the plurality of blocks, the processing device determines an endurance estimation of the selected block based on at least one of a time to erase the selected block or an error statistic for the selected block, and updates an endurance value associated with the selected block based on the endurance estimation for the selected block. The processing device receives a write instruction to the memory component and distributes the write instruction to one or more of the blocks based on the endurance values. Other embodiments are described.

Disclosed herein are techniques for management of a non-volatile memory device. In one example, an integrated circuit comprises a cache device and a management controller. The cache device is configured to store a first mapping between logical addresses and physical addresses of a first memory, the first mapping being a subset of mapping between logical addresses and physical addresses of the first memory stored in a second memory, and an access count associated with each of the physical addresses of the first mapping. The management controller is configured to: maintain access statistics of the first memory based on the access counts stored in the cache device; and determine the mapping between logical addresses and physical addresses stored in the second memory based on the access statistics and predicted likelihoods of at least some of the logical addresses receiving an access operation.

A controller of a memory system according to an embodiment manages, for each of a plurality of blocks, first information indicating whether a corresponding block is in use which indicates a state where the data is stored, second information indicating the number of erasures, and third information indicating a waiting time until next erasure. The controller executes first sequential write received from a host, and determines whether to execute processing of leveling the number of erasures for each of the plurality of blocks based on a first difference, a second difference, and a third difference when executing second sequential write received from the host.

A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

A data processing method and a corresponding system are provided. The method is implemented by a processor and includes: obtaining a to-be-processed I/O request, where the to-be-processed I/O request may include a first address, and the first address is a logical address of to-be-read, to-be-written, or to-be-erased data in a target SSD; performing address translation on the to-be-processed I/O request based on an FTL mapping table, to translate the first address into a second address, where the second address is used to indicate a physical address of the to-be-read, to-be-written, or to-be-erased data in the target SSD, and the FTL mapping table may be used to record a translation relationship between physical addresses and logical addresses in the n SSDs; sending a to-be-processed I/O request obtained after address translation is performed; and after a sleep duration is preset, querying a processing result of the to-be-processed I/O request.

Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.

Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

A method of operating a storage device, including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, includes determining a hotness of a logical address received with a write command and data to be written, from a host, based on the determined hotness being greater than a first hotness threshold, determining whether a wear level of the first memory region is greater than a wear threshold, and increasing the first hotness threshold and storing the data in the second memory region based on the wear level of the first memory region being greater than a threshold.

The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.