The subject matter described herein provides systems and techniques to counter a high write amplification in physical memory, to ensure the longevity of the physical memory, and to ensure that the physical memory wears in a more uniform manner. In this regard, aspects of this disclosure include the design of a Flash Translation Layer (FTL), which may manage logical to physical mapping of data within the physical memory. In particular, the FTL may be designed with a mapping algorithm, which uses reinforcement learning (RL) to optimize data mapping within the physical memory. The RL technique may use a Bellman equation with q-learning that may rely on a table being updated with entries that take into account at least one of a state, an action, a reward, or a policy. The RL technique may also make use a deep neural network to predict particular values of the table.

Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

A storage device includes a nonvolatile memory device, a memory controller, and a buffer memory. The memory controller determines a first memory block of the nonvolatile memory device, which is targeted for a read reclaim operation, and reads target data from a target area of the first memory block. The target data are stored in the buffer memory. The memory controller reads at least a portion of the target data stored in the buffer memory in response to a read request corresponding to at least a portion of the target area.

The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.

Aspects of a storage device including a controller are provided which identifies a bad, open block that causes subsequent erase operations to fail in closed blocks due to charge leakage following a previous program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.

Data tiering based on snapshots, including: receiving information describing, for data stored in a storage system, any snapshots associated with the data and any volumes storing the data; determining, from a plurality of storage tiers, a storage tier for the data based on the information; and storing the data in a storage device of the storage system associated with the storage tier.

Methods, systems, and devices for recovery of logical-to-physical (L2P) table information for a memory device are described. A memory system may detect an error in one or more pointers of the L2P table using an error detecting code that is uncorrectable using the code. The memory system may determine a set of candidate codewords for the set of bits, where each of the candidate codewords includes one or more corresponding candidate pointers, and check whether a candidate codeword is correct based on whether a logical address corresponding to a candidate pointer of the candidate codeword matches a logical address stored as metadata for a set of data at a physical address pointed to by the candidate pointer. The memory system may limit the set of candidate codewords or order the candidate codewords for evaluate to reduce a latency associated with identifying a correct candidate codeword.