An adder adds a noise signal, an input signal, and a feedback signal. A threshold determination unit compares an addition signal output from the adder with a predetermined threshold, and outputs an ignition pulse signal. A transient response unit causes transient response of the ignition pulse signal, and generates an output signal. An intensity adjustment unit is formed of a variable resistor provided on a feedback loop, adjusts intensity of the feedback signal, and inputs the feedback signal to the adder.

An adder adds a noise signal, an input signal, and a feedback signal. A threshold determination unit compares an addition signal output from the adder with a predetermined threshold, and outputs an ignition pulse signal. A transient response unit causes transient response of the ignition pulse signal, and generates an output signal. An intensity adjustment unit is formed of a variable resistor provided on a feedback loop, adjusts intensity of the feedback signal, and inputs the feedback signal to the adder.

A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.

Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

A high voltage inductive adder is disclosed. In some embodiments, the high voltage inductive adder comprising a first adder circuit and a second adder circuit. The first adder circuit including a first source; a first switch electrically coupled with the first source; a first transformer core; and a first plurality of primary windings wound about the first transformer core and electrically coupled with the first switch. The second adder circuit including a second source; a second switch electrically coupled with the second source; a second transformer core; and a second plurality of primary windings wound about the second transformer core and electrically coupled with the second switch. The high voltage inductive adder comprising one or more secondary windings wound around both the first transformer core and the second transformer core and an output coupled with the plurality of secondary windings.

A high voltage inductive adder is disclosed. In some embodiments, the high voltage inductive adder comprising a first adder circuit and a second adder circuit. The first adder circuit including a first source; a first switch electrically coupled with the first source; a first transformer core; and a first plurality of primary windings wound about the first transformer core and electrically coupled with the first switch. The second adder circuit including a second source; a second switch electrically coupled with the second source; a second transformer core; and a second plurality of primary windings wound about the second transformer core and electrically coupled with the second switch. The high voltage inductive adder comprising one or more secondary windings wound around both the first transformer core and the second transformer core and an output coupled with the plurality of secondary windings.

A high voltage inductive adder is disclosed. In some embodiments, the high voltage inductive adder comprising a first adder circuit and a second adder circuit. The first adder circuit including a first source; a first switch electrically coupled with the first source; a first transformer core; and a first plurality of primary windings wound about the first transformer core and electrically coupled with the first switch. The second adder circuit including a second source; a second switch electrically coupled with the second source; a second transformer core; and a second plurality of primary windings wound about the second transformer core and electrically coupled with the second switch. The high voltage inductive adder comprising one or more secondary windings wound around both the first transformer core and the second transformer core and an output coupled with the plurality of secondary windings.

A high voltage inductive adder is disclosed. In some embodiments, the high voltage inductive adder comprising a first adder circuit and a second adder circuit. The first adder circuit including a first source; a first switch electrically coupled with the first source; a first transformer core; and a first plurality of primary windings wound about the first transformer core and electrically coupled with the first switch. The second adder circuit including a second source; a second switch electrically coupled with the second source; a second transformer core; and a second plurality of primary windings wound about the second transformer core and electrically coupled with the second switch. The high voltage inductive adder comprising one or more secondary windings wound around both the first transformer core and the second transformer core and an output coupled with the plurality of secondary windings.

An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.

A sensor includes groups of sense elements coupled to one another to form multiple Wheatstone bridges, each being configured to produce an output voltage across first and second output nodes. A signal interface circuit for the sensor includes switched capacitor structures, one each of the switched capacitor structures being associated with one each of the Wheatstone bridges. Each switched capacitor structure includes a capacitor having first and second terminals, a first switch for selectively interconnecting the first node of an associated Wheatstone bridge with the first terminal of the capacitor, and a second switch for selectively interconnecting the second node of the associated Wheatstone bridge with the second terminal of the capacitor. A switch state element toggles the first and second switches between a charge state and a readout state to provide a readout voltage that is equivalent to a summation of the voltage outputs of the Wheatstone bridges.