A semiconductor device with high arithmetic performance is provided. The semiconductor device employs the translinear principle, and the semiconductor device includes first to tenth transistors each including a metal oxide in a channel formation region and a first capacitor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor is electrically connected to a second terminal of the second transistor and a gate of the second transistor through the first capacitor. The second terminal of the second transistor is electrically connected to first terminals of the fourth and the seventh transistors and gates of the fifth and the eighth transistors. A gate of the seventh transistor is electrically connected to first terminals of the fifth and the sixth transistors, and a gate of the tenth transistor is electrically connected to first terminals of the eighth and the ninth transistors.

Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.

Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.

A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.

A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.

An inverting amplifier creates a voltage C using a reference voltage (voltage B) as a reference point. An adder composed of two input inverting amplifier circuits ultimately creates a voltage D by carrying out weighted addition of the voltage A and the voltage C. By using the voltage D created by an input front-end circuit, the internal functions of the control IC can prevent the operating points and control amounts for each function from being different relative to the input voltage and make it possible to distinguish voltage within the control IC from zero voltage when the lowest input voltage is received.

An inverting amplifier creates a voltage C using a reference voltage (voltage B) as a reference point. An adder composed of two input inverting amplifier circuits ultimately creates a voltage D by carrying out weighted addition of the voltage A and the voltage C. By using the voltage D created by an input front-end circuit, the internal functions of the control IC can prevent the operating points and control amounts for each function from being different relative to the input voltage and make it possible to distinguish voltage within the control IC from zero voltage when the lowest input voltage is received.

A technique with which a change in power frequency can be suppressed. A power system stabilizer issues a control command to a first storage battery among a plurality of first power generators and the first storage battery that are connected to an isolated island system via a first tie-line. The power system stabilizer includes a parameter determination unit and a control block unit. The parameter determination unit obtains, on the basis of operation information, a rate-of-change limit value that indicates a limit to be imposed on a total value of changes in the overall output of first power generators in operation. The control block unit generates a command value to be given to the first storage battery on the basis of an interconnection point power flow value measured on the first tie-line and the rate-of-change limit value obtained by the parameter determination unit.