An arithmetic apparatus includes input line pairs and a multiply-accumulate device. A signal pair is input to the input line pairs within an input period. The multiply-accumulate device includes multiplication units, an accumulation unit, a charging unit, and an output unit. The multiplication units generate a positive weight charge and a negative weight charge. The accumulation unit accumulates the positive weight charge and the negative weight charge. The charging unit charges the accumulation unit after the input period. The output unit performs, after charging starts, threshold determination using a predetermined threshold value on a voltage of the accumulation unit, to thereby output a positive multiply-accumulate signal representing a sum of positive weight product values and a negative multiply-accumulate signal representing a sum of negative weight product values.

An arithmetic apparatus includes input line pairs and a multiply-accumulate device. A signal pair is input to the input line pairs within an input period. The multiply-accumulate device includes multiplication units, an accumulation unit, a charging unit, and an output unit. The multiplication units generate a positive weight charge and a negative weight charge. The accumulation unit accumulates the positive weight charge and the negative weight charge. The charging unit charges the accumulation unit after the input period. The output unit performs, after charging starts, threshold determination using a predetermined threshold value on a voltage of the accumulation unit, to thereby output a positive multiply-accumulate signal representing a sum of positive weight product values and a negative multiply-accumulate signal representing a sum of negative weight product values.

A multiplexing device for a digital-to-analog conversion circuit and an analog-to-digital conversion circuit in a storage and calculation integrated chip, comprising a digital-to-analog conversion circuit (DAC) module, an analog vector-matrix multiplication operation circuit(AMAC) module, an analog-to-digital conversion circuit(ADC) module, a first many-to-one multiplexer (M1-MUX) module, a second M1-MUX module, a first one-to-many multiplexer (1M-MUX) module, a second 1M-MUX module, and a switching transistor module. At an AMAC input end, each DAC corresponds to a plurality of input ends and is shared with the first 1M-MUX module in a time multiplexing mode by means of the first M1-MUX module; at an AMAC output end, each ADC corresponds to a plurality of output ends, and is shared with the second 1M-MUX module in a time multiplexing mode by means of the second M1-MUX module; the number of DACs and ADCs is reduced, and the chip area is reduced.

A semiconductor device capable of convolutional processing with low power consumption is provided. In the semiconductor device, a first circuit includes a first holding portion and a first transistor, and a second circuit includes a second holding portion and a second transistor. The first and second circuits are electrically connected to first and second input wirings and first and second wirings. The first holding portion has a function of holding a first current flowing through the first transistor, and the second holding portion has a function of holding a second current flowing through the second transistor. The first and second currents are determined by a filter value used for convolutional processing. When a potential corresponding to image data subjected to convolutional processing is input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The amount of current output from the first and second circuits to the first wiring or the second wiring is determined by the filter value and the image data.

A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.

An analog vector-matrix multiplication circuit is achieved by using a programmable storage device array. In a programmable semiconductor device array, gates of all of programmable semiconductor devices of each row are all connected to the same analog voltage input end. M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input ends. Drains (or sources) of all of programmable semiconductor devices of each column are all connected to the same bias voltage input end. N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input ends. Sources (or drains) of all of programmable semiconductor devices of each column are all connected to the same analog current output end. The N columns of programmable semiconductor devices are correspondingly connected to N analog current output ends. Threshold voltages of the programmable semiconductor devices are controlled, such that each programmable semiconductor device can be regarded as a variable equivalent analog weight, thereby achieving the matrix multiplication function.

An analog vector-matrix multiplication circuit is achieved by using a programmable storage device array. In a programmable semiconductor device array, gates of all of programmable semiconductor devices of each row are all connected to the same analog voltage input end. M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input ends. Drains (or sources) of all of programmable semiconductor devices of each column are all connected to the same bias voltage input end. N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input ends. Sources (or drains) of all of programmable semiconductor devices of each column are all connected to the same analog current output end. The N columns of programmable semiconductor devices are correspondingly connected to N analog current output ends. Threshold voltages of the programmable semiconductor devices are controlled, such that each programmable semiconductor device can be regarded as a variable equivalent analog weight, thereby achieving the matrix multiplication function.

The present disclosure provides a multiplication and accumulation circuit based on radix-4 booth code and differential weight storage. The circuit includes an input data encoding circuit, a differential weight storage circuit, an integral calculation circuit and a differential ADC circuit. The input data encoding circuit is configured to encode original input data. The differential weight storage circuit is configured to store weight values, and multiply the original input data after being encoded by the weight values stored to obtain multiplication results. The integral calculation circuit is configured to respectively accumulate a positive value and a negative value of each multiplication result. The differential ADC circuit is configured to perform analog-to-digital conversion on a difference between accumulated results of the positive values and the negative values to obtain a digital multiplication and accumulation result.

A neural network device includes a shift register circuit, a control circuit, and a processing circuit. The shift register circuit includes registers configured to, in each cycle of cycles, transfer stored data to a next register and store new data received from a previous register to a current register. The control circuit is configured to sequentially input data of input activations included in an input feature map into the shift register circuit in a preset order. The processing circuit, includes crossbar array groups that receive input activations from at least one of the registers and perform a multiply-accumulate (MAC) operation with respect to the received input activation and weights, is configured to accumulate and add at least some operation results output from the crossbar array groups in a preset number of cycles to obtain an output activation in an output feature map.

An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.