A first circuit is configured to split a first integer value into a first coarse value and a first fine value, and split a second integer value into a second coarse value and a second fine value. A second circuit performs an analog multiply and accumulate (MAC) operation on the first and second coarse values to produce a first analog output, perform an analog MAC operation on the first coarse value and the second fine value to produce a second analog output, perform an analog MAC operation on the first fine value and the second coarse value to produce a third analog output, and perform an analog MAC operation on the first and second fine values together to produce a fourth analog output. A third circuit is configured to perform analog-to-digital (A/D) conversion on and combine the analog output signals to produce a reconstructed digital output signal.

A first circuit is configured to split a first integer value into a first coarse value and a first fine value, and split a second integer value into a second coarse value and a second fine value. A second circuit performs an analog multiply and accumulate (MAC) operation on the first and second coarse values to produce a first analog output, perform an analog MAC operation on the first coarse value and the second fine value to produce a second analog output, perform an analog MAC operation on the first fine value and the second coarse value to produce a third analog output, and perform an analog MAC operation on the first and second fine values together to produce a fourth analog output. A third circuit is configured to perform analog-to-digital (A/D) conversion on and combine the analog output signals to produce a reconstructed digital output signal.

A capacitive multiplier includes, in part, a multitude of capacitors disposed along S rows and T columns. The capacitors disposed in the ith column are coupled to one another and are configured to be coupled to or uncoupled from capacitors disposed in the column T via an ith switch, where i ranges from 1 to (T-1). The capacitive multiplier further includes, in part, a timing controller configured to generate (T-1) control signals each of which is associated with one of (T-1) switches. The timing controller generates the (T-1) control signals in sequence such that the ith switch is closed before (i+1)th switch opens, and the ith switch is opened before closing the (i+1)th switch. In response to closing of the ith switch, the capacitors in the ith column are coupled to capacitors in column T to share and distribute their charges.

A capacitive multiplier includes, in part, a multitude of capacitors disposed along S rows and T columns. The capacitors disposed in the ith column are coupled to one another and are configured to be coupled to or uncoupled from capacitors disposed in the column T via an ith switch, where i ranges from 1 to (T-1). The capacitive multiplier further includes, in part, a timing controller configured to generate (T-1) control signals each of which is associated with one of (T-1) switches. The timing controller generates the (T-1) control signals in sequence such that the ith switch is closed before (i+1)th switch opens, and the ith switch is opened before closing the (i+1)th switch. In response to closing of the ith switch, the capacitors in the ith column are coupled to capacitors in column T to share and distribute their charges.

A memory device and a computing method thereof are provided in the present disclosure. The computing method includes the following steps. A plurality of input-values of a model computation are respectively received through a plurality of first-word-lines of a memory array. Inverted logic values of the input-values are respectively received through a plurality of second-word-lines. The input-values are respectively received through a plurality of first-bit-lines. The inverted logic values are respectively received through a plurality of second-bit-lines. Logic XNOR operation is performed according to each of the input-values and each of the inverted values to obtain a first computation result, and multiplied with one of self-coefficients or one of mutual coefficients of the model computation to obtain a plurality of output-values. The output-values are outputted through a plurality of common-source-lines.

A memory device and a computing method thereof are provided in the present disclosure. The computing method includes the following steps. A plurality of input-values of a model computation are respectively received through a plurality of first-word-lines of a memory array. Inverted logic values of the input-values are respectively received through a plurality of second-word-lines. The input-values are respectively received through a plurality of first-bit-lines. The inverted logic values are respectively received through a plurality of second-bit-lines. Logic XNOR operation is performed according to each of the input-values and each of the inverted values to obtain a first computation result, and multiplied with one of self-coefficients or one of mutual coefficients of the model computation to obtain a plurality of output-values. The output-values are outputted through a plurality of common-source-lines.

A multiply and accumulate calculation device including a variable resistor array unit having a plurality of variable resistance elements, a reference array unit having a reference resistance element having a fixed resistance value, a signal input unit that generates an input signal from input data, and inputs the input signal to the variable and reference resistance elements, a first detection unit that detects a current flowing through the variable resistor array unit, based on the input signal applied to the variable resistance elements, a second detection unit that detects a current flowing through the reference array unit, based on the input signal applied to the reference resistance element, and a correction calculation unit that performs a predetermined calculation on the output from the first detection unit, based on the output from the second.

A multiply and accumulate calculation device including a variable resistor array unit having a plurality of variable resistance elements, a reference array unit having a reference resistance element having a fixed resistance value, a signal input unit that generates an input signal from input data, and inputs the input signal to the variable and reference resistance elements, a first detection unit that detects a current flowing through the variable resistor array unit, based on the input signal applied to the variable resistance elements, a second detection unit that detects a current flowing through the reference array unit, based on the input signal applied to the reference resistance element, and a correction calculation unit that performs a predetermined calculation on the output from the first detection unit, based on the output from the second.

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.

Disclosed is an apparatus for computationally intensive applications, such as information technology applications requiring computational power. Disclosed is an apparatus arranged to provide an analog signal to at least one input of an analog compute-in-memory resistive matrix comprised in said apparatus, and to receive a digital signal from at least one direct-drive analog-to-digital converter in the output of said at least one analog compute-in-memory resistive matrix.