An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.

Methods and devices are disclosed relating improved articular models, implant components, and related guide tools and procedures. In addition, methods and devices are disclosed relating articular models, implant components, and/or related guide tools and procedures that include one or more features derived from patient-data, for example, images of the patient's joint. The data can be used to create a model for analyzing a patient's joint and to devise and evaluate a course of corrective action. The data also can be used to create patient-adapted implant components and related tools and procedures.

Methods, computer systems, and computer-readable storage media for generating graphical representations of health-related variables are provided. The graphical representations include a first body-image representation of a user at a current period of time. The graphical representations also include a second body-image representation that represents the user at a future period of time, the user in a simulated clinical “what-if” scenario, or members of the population-at-large that share similar demographic traits with the user.

Systems and methods for collecting and processing physical space data for use while performing an image-guided surgical (IGS) procedure are provided. The system and method includes obtaining a computer model of a non-rigid structure of interest in a patient and performing a rigid alignment of the computer model and surface data in a patient space associated with at least a portion of the non-rigid structure. The system and method also include computing a deformation of the computer model that provides a non-rigid alignment of the computer model and surface data, the deformation computed using a set of boundary conditions defined for each node of the computer model based on the rigid alignment and a kernel function. Additionally, the system and method can include displaying data for facilitating the IGS procedure based on the deformation.

An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.

A multiply-accumulate calculation device includes a plurality of redundancy circuits including a plurality of multiply calculation elements and configured to input a plurality of first intermediate signals generated from an input signal corresponding to an input value to the plurality of multiply calculation elements and generate and output a plurality of second intermediate signals, each of which corresponds to a signal obtained by multiplying each of the plurality of first intermediate signals by a weight in each of the plurality of multiply calculation elements, a plurality of output signal generation circuits configured to generate output signals on the basis of the plurality of second intermediate signals and output the output signals, and an accumulate calculation circuit configured to calculate a sum of the output signals output by the plurality of output signal generation circuits.

An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

A semiconductor device that restores degraded data is provided. The semiconductor device includes a first circuit, a storage portion, and an arithmetic portion. The first circuit includes a current source and a first switch. The storage portion includes a first transistor and a first capacitor. The arithmetic portion includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. When data retained in the arithmetic portion is restored, the first transistor is turned on, and the data retained in the storage portion is supplied to the control terminal of the first switch through the first transistor. The first switch is brought into an on state or an off state in accordance with the data and supplies current from the current source to the arithmetic portion through the second transistor to supply electric charge to a retention portion of the arithmetic portion.

A semiconductor device that restores degraded data is provided. The semiconductor device includes a first circuit, a storage portion, and an arithmetic portion. The first circuit includes a current source and a first switch. The storage portion includes a first transistor and a first capacitor. The arithmetic portion includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. When data retained in the arithmetic portion is restored, the first transistor is turned on, and the data retained in the storage portion is supplied to the control terminal of the first switch through the first transistor. The first switch is brought into an on state or an off state in accordance with the data and supplies current from the current source to the arithmetic portion through the second transistor to supply electric charge to a retention portion of the arithmetic portion.

A semiconductor device capable of convolutional processing with low power consumption is provided. In the semiconductor device, a first circuit includes a first holding portion and a first transistor, and a second circuit includes a second holding portion and a second transistor. The first and second circuits are electrically connected to first and second input wirings and first and second wirings. The first holding portion has a function of holding a first current flowing through the first transistor, and the second holding portion has a function of holding a second current flowing through the second transistor. The first and second currents are determined by a filter value used for convolutional processing. When a potential corresponding to image data subjected to convolutional processing is input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The amount of current output from the first and second circuits to the first wiring or the second wiring is determined by the filter value and the image data.