A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

An arithmetic circuit includes a variable resistance element having three terminals of a first terminal, a second terminal, and a third terminal and configured such that the resistance value is variable, an input line connected to the first terminal, a capacitor connected to the second terminal and provided between the second terminal and the reference potential, a first switching element connected to the third terminal, a wiring connected to the third terminal through the first switching element, a second switching element connected to a first end of the wiring, and a third switching element connected to a second end of the wiring.

An arithmetic circuit includes a variable resistance element having three terminals of a first terminal, a second terminal, and a third terminal and configured such that the resistance value is variable, an input line connected to the first terminal, a capacitor connected to the second terminal and provided between the second terminal and the reference potential, a first switching element connected to the third terminal, a wiring connected to the third terminal through the first switching element, a second switching element connected to a first end of the wiring, and a third switching element connected to a second end of the wiring.

Embodiments include a system for determining cardiovascular information for a patient. The system may include at least one computer system configured to receive patient-specific data regarding a geometry of the patient's heart, and create a three-dimensional model representing at least a portion of the patient's heart based on the patient-specific data. The at least one computer system may be further configured to create a physics-based model relating to a blood flow characteristic of the patient's heart and determine a fractional flow reserve within the patient's heart based on the three-dimensional model and the physics-based model.

Embodiments include a system for determining cardiovascular information for a patient. The system may include at least one computer system configured to receive patient-specific data regarding a geometry of the patient's heart, and create a three-dimensional model representing at least a portion of the patient's heart based on the patient-specific data. The at least one computer system may be further configured to create a physics-based model relating to a blood flow characteristic of the patient's heart and determine a fractional flow reserve within the patient's heart based on the three-dimensional model and the physics-based model.

A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell. Then, a third current flows from the second circuit to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the amount of the potential change and the first current.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fifth circuits. Each of the first to fourth circuits includes first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first circuit to the fourth circuit are electrically connected to each other in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell through the first wiring, the first current generation circuit, and the third wiring, and is electrically connected to the first input terminal and the sixth circuit through the second wiring. The second cell is electrically connected to the first output terminal through the second current generation circuit. Note that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as an arithmetic circuit of a function system. The first cell performs an arithmetic operation of a product, and the second cell retains the result of the arithmetic operation.

Embodiments include a system for determining cardiovascular information for a patient. The system may include at least one computer system configured to receive patient-specific data regarding a geometry of the patient's heart, and create a three-dimensional model representing at least a portion of the patient's heart based on the patient-specific data. The at least one computer system may be further configured to create a physics-based model relating to a blood flow characteristic of the patient's heart and determine a fractional flow reserve within the patient's heart based on the three-dimensional model and the physics-based model.