Patent classifications
G06K7/016
Method of calibrating a clock of a chip card circuit, and associated system
A calibration method for calibrating a clock of a circuit for a smart card, which includes operations for: at a first instant, storing (S310) first time data from a terminal in the clock; at a second instant, reading (S320) second time data from the clock and corresponding to the first time data incremented by the clock as a function of a first duration between the first instant and the second instant; comparing (S330) the second time data with third time data corresponding to the first time data incremented, by the terminal or by a remote server, as a function of the first duration between the first instant and the second instant; as a function of the result of the comparison, calculating (S340) first calibration data; and storing (S350) the first calibration data in the clock. The reading of the second time data may be in a contactless manner.
Method of calibrating a clock of a chip card circuit, and associated system
A calibration method for calibrating a clock of a circuit for a smart card, which includes operations for: at a first instant, storing (S310) first time data from a terminal in the clock; at a second instant, reading (S320) second time data from the clock and corresponding to the first time data incremented by the clock as a function of a first duration between the first instant and the second instant; comparing (S330) the second time data with third time data corresponding to the first time data incremented, by the terminal or by a remote server, as a function of the first duration between the first instant and the second instant; as a function of the result of the comparison, calculating (S340) first calibration data; and storing (S350) the first calibration data in the clock. The reading of the second time data may be in a contactless manner.
RFID tag clock frequency reduction during tuning
An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.
RFID tag clock frequency reduction during tuning
An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.
RFID tag clock frequency reduction during tuning
An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.
RFID tag clock frequency reduction during tuning
An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.
MULTI-PROTOCOL RFID SYSTEM
A multi-protocol RFID interrogating system employs a synchronization technique (step-lock) for a backscatter RFID system that allows simultaneous operation of closely spaced interrogators. The multi-protocol RFID interrogating system can communicate with backscatter transponders having different output protocols and with active transponders including: Title 21 compliant RFID backscatter transponders; IT2000 RFID backscatter transponders that provide an extended mode capability beyond Title 21; EGOTM RFID backscatter transponders, SEGOTM RFID backscatter transponders; ATA, ISO, ANSI AAR compliant RFID backscatter transponders; and IAG compliant active technology transponders. The system implements a step-lock operation, whereby adjacent interrogators are synchronized to ensure that all downlinks operate within the same time frame and all uplinks operate within the same time frame, to eliminate downlink on uplink interference.
MULTI-PROTOCOL RFID SYSTEM
A multi-protocol RFID interrogating system employs a synchronization technique (step-lock) for a backscatter RFID system that allows simultaneous operation of closely spaced interrogators. The multi-protocol RFID interrogating system can communicate with backscatter transponders having different output protocols and with active transponders including: Title 21 compliant RFID backscatter transponders; IT2000 RFID backscatter transponders that provide an extended mode capability beyond Title 21; EGOTM RFID backscatter transponders, SEGOTM RFID backscatter transponders; ATA, ISO, ANSI AAR compliant RFID backscatter transponders; and IAG compliant active technology transponders. The system implements a step-lock operation, whereby adjacent interrogators are synchronized to ensure that all downlinks operate within the same time frame and all uplinks operate within the same time frame, to eliminate downlink on uplink interference.
SYSTEMS, METHODS, AND COMPUTER-ACCESSIBLE MEDIUMS FOR REPRESSING OR TURNING OFF THE READ OF A DIGITAL TAG
An exemplary system, method, and computer-accessible medium can include, for example, storing on a first device a digital tag, the tag configured to be associated with at least one application on a second device, such that receipt of the tag on the second device launches the application on the second device; and emitting from the first device to a second device the digital tag; wherein the application on the second device is configured to launch in a special state when the second device is in at least one state from a pre-determined list of states.
VEHICULAR SYSTEM AND TAG COMMUNICATION METHOD
A vehicular system (1) detects a magnetic marker (10) laid in a road and wirelessly communicates with a wireless tag (15) attached to the magnetic marker (10). The system includes a measuring unit (2) which detects the magnetic marker (10) by sensing magnetism, a tag reader (34) which executes a communication process with the wireless tag (15), and a control unit (32) which sets a communication start point as a start point of the communication process by the tag reader (34). The control unit (32) sets, as a communication start point, a time after a lapse of specified time with reference to a time point of detection at which the measuring unit (2) detects the magnetic marker (10). Upon reading information from the wireless tag (15), the tag reader (34) terminates communication, thereby shortening a communication time.