A neuromorphic neuron apparatus includes an accumulation block and an output generation block. The apparatus has a current state variable corresponding to previously received one or more signals. The output generation block is configured to use an activation function for generating a current output value based on the current state variable. The accumulation block is configured to repeatedly: compute an adjustment of the current state variable using the current output value and a correction function indicative of a decay behaviour of a time constant of the apparatus; receive a current signal; update the current state variable using the computed adjustment and the received signal, the updated state variable becoming the current state variable; and cause the output generation block to generate a current output value based on the current state variable.

A neuromorphic system includes a first neuromorphic layer configured to perform a forward operation with an input signal and a first weight, a first operation circuit configured to perform a first operation on a result of the forward operation of the first neuromorphic layer, a second neuromorphic layer configured to perform a forward operation with an output signal of the first operation circuit and a second weight, a second operation circuit configured to perform a second operation on a result of the forward operation of the second neuromorphic layer, a first weight adjustment amount calculation circuit configured to calculate a first weight adjustment amount, and a second weight adjustment amount calculation circuit configured to calculate a second weight adjustment amount.

An exemplary aspect relates to the field of pattern recognition, and in one exemplary embodiment to the field of image recognition. More specifically, an embodiment relates to the use of deep neural networks for image recognition and how these kinds of pattern classification structures may be augmented in order to become aware of the available computation time, and the available computational resources so as to appropriately adjust the computational complexity of their associated algorithms and consequently their need for computing resources. The methods and systems described herein at least enable more economical and flexible implementations for porting to embedded computing frameworks by respecting their computational resources.

According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

Processing a neural network data flow graph having a set of nodes and a set of edges. An insertion point is determined for a memory reduction or memory restoration operation. The determination is based on computing tensor timing slacks (TTS) for a set of input tensors; compiling a candidate list (SI) of input tensors, from the set of input tensors, using input tensors having corresponding TTS values larger than a threshold value (thTTS); filtering the SI to retain input tensors whose size meets a threshold value (thS); and determining an insertion point for the operation using the SI based on the filtering. A new data flow graph is generated or an existing one is modified using this process.

Processing a neural network data flow graph having a set of nodes and a set of edges. An insertion point is determined for a memory reduction or memory restoration operation. The determination is based on computing tensor timing slacks (TTS) for a set of input tensors; compiling a candidate list (SI) of input tensors, from the set of input tensors, using input tensors having corresponding TTS values larger than a threshold value (thTTS); filtering the SI to retain input tensors whose size meets a threshold value (thS); and determining an insertion point for the operation using the SI based on the filtering. A new data flow graph is generated or an existing one is modified using this process.

In a data processing method, a processing device obtains a first neural network model and an available resource state of a terminal device, and determines a second neural network model based on the first neural network model and the available resource state. An appropriate model size is determined based on the available resource state, and a part of the first neural network model is selected, based on the determined model size, as the second neural network model on which data processing is to be performed.

In a data processing method, a processing device obtains a first neural network model and an available resource state of a terminal device, and determines a second neural network model based on the first neural network model and the available resource state. An appropriate model size is determined based on the available resource state, and a part of the first neural network model is selected, based on the determined model size, as the second neural network model on which data processing is to be performed.

Systems and/or devices for efficient and intuitive methods for implementing artificial neural networks specifically designed for parallel AI processing are provided herein. In various implementations, the disclosed systems, devices, and methods complement or replace conventional systems, devices, and methods for parallel neural processing that (a) greatly reduce neural processing time necessary to process more complex problem sets; (b) implement neuroplasticity necessary for self-learning; and (c) introduce the concept and application of implicit memory, in addition to explicit memory, necessary to imbue an element of intuition. With these properties, implementations of the disclosed invention make it possible to emulate human consciousness or awareness.

A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.