Patent classifications
G06N3/06
Convolutional neural network processor and data processing method thereof
A convolutional neural network processor includes an information decode unit and a convolutional neural network inference unit. The information decode unit is configured to receive a program input and weight parameter inputs and includes a decoding module and a parallel processing module. The decoding module receives the program input and produces an operational command according to the program input. The parallel processing module is electrically connected to the decoding module, receives the weight parameter inputs and includes a plurality of parallel processing sub-modules for producing a plurality of weight parameter outputs. The convolutional neural network inference unit is electrically connected to the information decode unit and includes a computing module. The computing module is electrically connected to the parallel processing module and produces an output data according to an input data and the weight parameter outputs.
Convolutional neural network processor and data processing method thereof
A convolutional neural network processor includes an information decode unit and a convolutional neural network inference unit. The information decode unit is configured to receive a program input and weight parameter inputs and includes a decoding module and a parallel processing module. The decoding module receives the program input and produces an operational command according to the program input. The parallel processing module is electrically connected to the decoding module, receives the weight parameter inputs and includes a plurality of parallel processing sub-modules for producing a plurality of weight parameter outputs. The convolutional neural network inference unit is electrically connected to the information decode unit and includes a computing module. The computing module is electrically connected to the parallel processing module and produces an output data according to an input data and the weight parameter outputs.
Generative adversarial network device and training method thereof
A generative adversarial network device and a training method thereof. The generative adversarial network device includes a generator and a discriminator. The generator is configured to generate a first sample according to an input data; the discriminator is coupled to the generator, and is configured to receive the first sample and be trained based on the first sample; the generator includes a first memristor array serving as a first weight array. The generative adversarial network device can omit a process of adding noise to fake samples generated by the generator, thereby saving training time, reducing resource consumption and improving training speed of the generative adversarial network.
Systems and methods for removing identifiable information
Systems and methods for censoring text characters in text-based data are provided. In some embodiments, an artificial intelligence system may be configured to receive text-based data and store the text-based data in a database. The artificial intelligence system may be configured to receive a list of target pattern types identifying sensitive data and receive censorship rules for the target pattern types determining target pattern types requiring censorship. The artificial intelligence system may be configured to assemble a computer-based model related to a received target pattern type in the list of target pattern types. The artificial intelligence system may be configured to use a computer-based model to identify a target data pattern corresponding to the received target pattern type within the text-based data, identify target characters within the target data pattern, and to assign an identification token to the target characters.
METHOD FOR MULTI-TASK-BASED PREDICTING MASSIVEUSER LOADS BASED ON MULTI-CHANNEL CONVOLUTIONAL NEURAL NETWORK
A method for multi-task-based predicting massive-user loads based on a multi-channel convolutional neural network, and belongs to the technical field of electric power systems. The method includes clustering all residential users into a plurality of clusters with different daily average electricity consumption modes by adopting an agglomerative hierarchical clustering method. Corresponding input data sets are constructed for various clusters by adopting a multi-channel-based multi-source input fusion method. Then, a multi-task-based load prediction model based on a convolutional neural network is established for each of the clusters. Load prediction values for different users in the corresponding cluster are output in parallel by each model to eventually obtain load prediction results of all of the residential users. In the present disclosure, the load predictions for all of the residential users are completed, the average prediction accuracy is improved, the number of modeling times and the accumulative operation time are greatly reduced.
METHOD FOR MULTI-TASK-BASED PREDICTING MASSIVEUSER LOADS BASED ON MULTI-CHANNEL CONVOLUTIONAL NEURAL NETWORK
A method for multi-task-based predicting massive-user loads based on a multi-channel convolutional neural network, and belongs to the technical field of electric power systems. The method includes clustering all residential users into a plurality of clusters with different daily average electricity consumption modes by adopting an agglomerative hierarchical clustering method. Corresponding input data sets are constructed for various clusters by adopting a multi-channel-based multi-source input fusion method. Then, a multi-task-based load prediction model based on a convolutional neural network is established for each of the clusters. Load prediction values for different users in the corresponding cluster are output in parallel by each model to eventually obtain load prediction results of all of the residential users. In the present disclosure, the load predictions for all of the residential users are completed, the average prediction accuracy is improved, the number of modeling times and the accumulative operation time are greatly reduced.
Neural network computation circuit including non-volatile semiconductor memory element
A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.
Programmable computations in direct memory access engine
To perform complex arithmetic operations in neural networks without compromising the performance of the neural network accelerator, a programmable computation unit is integrated with a direct memory access (DMA) engine that is used to exchange neural network parameters between the neural network accelerator and system memory. The DMA engine may include a calculation circuit operable to perform a multiply-and-add calculation on a set of operands, and an operand selector circuit operable to select a source for each operand of the calculation circuit. The DMA engine may also include a control circuit operable to retrieve a meta-descriptor for performing a computation, configure the operand selector circuit based on the meta-descriptor, and use the calculation circuit to perform the computation based on the meta-descriptor to generate a computation result.
Programmable computations in direct memory access engine
To perform complex arithmetic operations in neural networks without compromising the performance of the neural network accelerator, a programmable computation unit is integrated with a direct memory access (DMA) engine that is used to exchange neural network parameters between the neural network accelerator and system memory. The DMA engine may include a calculation circuit operable to perform a multiply-and-add calculation on a set of operands, and an operand selector circuit operable to select a source for each operand of the calculation circuit. The DMA engine may also include a control circuit operable to retrieve a meta-descriptor for performing a computation, configure the operand selector circuit based on the meta-descriptor, and use the calculation circuit to perform the computation based on the meta-descriptor to generate a computation result.
Convolutional operation device with dimensional conversion
A convolutional operation device for performing convolutional neural network processing includes an input sharing network including first and second input feature map registers configured to shift each input feature map, which is inputted in row units, in a row or column direction and output the shifted input feature map and arranged in rows and columns, a first MAC array connected to the first input feature map registers, an input feature map switching network configured to select one of the first and second input feature map registers, a second MAC array connected to one selected by the input feature map switching network among the first and second input feature map registers, and an output shift network configured to shift the output feature map from the first MAC array and the second MAC array to transmit the shifted output feature map to an output memory.