An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to generate a reference demographic impression distribution based on first impressions of logged impressions at a first server corresponding to first client devices, access an inaccurate demographic impression distribution based on second impressions corresponding to second client devices, determine an estimated demographic impression distribution based on an inaccurate demographic impression distribution, the estimated demographic impression distribution representative of the second impressions distributed across the different demographic segments, determine a matrix based on a reference demographic impression distribution and Lagrange multiplier values, determine an error indicator value based on the matrix, generate, in response to the error indicator value satisfying a threshold, an accuracy-improved demographic impression distribution, and store, in the at least one memory, the accuracy-improved demographic impression distribution.

A processor package comprises at least one Baum-Welch core. The Baum-Welch core comprises a likelihood-value generator, an emission-probability generator, and a transition-probability generator. The likelihood-value generator generates forward values and backward values for a set of observations. The emission-probability generator generates emission probabilities for the set of observations. The transition-probability generator generates transition probabilities for the set of observations. Furthermore, the BW core is to generate, in parallel, at least two types of probability values from the group consisting of forward values, backward values, emission probabilities, and transition probabilities. Other embodiments are described and claimed.

Disclosed is a neural network structure enabling efficient training of the network and a method thereto. The structure is a ladder-type structure wherein one or more lateral input(s) is/are taken to decoding functions. By minimizing one or more cost function(s) belonging to the structure the neural network structure may be trained in an efficient way.

Techniques and a system for quantum computing device modeling and design are provided. In one example, a system includes a modeling component and a simulation component. The modeling component models a quantum device element of a quantum computing device as an electromagnetic circuit element to generate electromagnetic circuit data for the quantum computing device. The simulation component simulates the quantum computing device using the electromagnetic circuit data to generate response function data indicative of a response function for the quantum computing device. Additionally or alternatively, a Hamiltonian is constructed based on the response function.

This disclosure is directed to an apparatus for intelligent matching of disparate input data received from disparate input data systems in a complex computing network for establishing targeted communication to a computing device associated with the intelligently matched disparate input data.

This disclosure is directed to an apparatus for intelligent matching of disparate input data received from disparate input data systems in a complex computing network for establishing targeted communication to a computing device associated with the intelligently matched disparate input data.

Embodiments of the present disclosure relate to splitting input data into smaller units for loading into a data buffer and neural engines in a neural processor circuit for performing neural network operations. The input data of a large size is split into slices and each slice is again split into tiles. The tile is uploaded from an external source to a data buffer inside the neural processor circuit but outside the neural engines. Each tile is again split into work units sized for storing in an input buffer circuit inside each neural engine. The input data stored in the data buffer and the input buffer circuit is reused by the neural engines to reduce re-fetching of input data. Operations of splitting the input data are performed at various components of the neural processor circuit under the management of rasterizers provided in these components.

Embodiments of the present disclosure relate to splitting input data into smaller units for loading into a data buffer and neural engines in a neural processor circuit for performing neural network operations. The input data of a large size is split into slices and each slice is again split into tiles. The tile is uploaded from an external source to a data buffer inside the neural processor circuit but outside the neural engines. Each tile is again split into work units sized for storing in an input buffer circuit inside each neural engine. The input data stored in the data buffer and the input buffer circuit is reused by the neural engines to reduce re-fetching of input data. Operations of splitting the input data are performed at various components of the neural processor circuit under the management of rasterizers provided in these components.

This disclosure is directed to an apparatus for intelligent matching of disparate input data received from disparate input data systems in a complex computing network for establishing targeted communication to a computing device associated with the intelligently matched disparate input data.

This disclosure is directed to an apparatus for intelligent matching of disparate input data received from disparate input data systems in a complex computing network for establishing targeted communication to a computing device associated with the intelligently matched disparate input data.