An image processing apparatus including: an input unit configured to input image data of a target frame; a first processing unit configured to perform a first processing for output image data of a reference frame related to the target frame, which is stored in the memory, to change positions of pixels in the output image data; an image processing unit configured to perform image processing for the image data of the target frame input by the input unit based on the output image data of the reference frame processed by the first processing unit; and a second processing unit configured to perform a second processing, the second processing is according to the first processing, for the image data of the target frame for which image processing has been performed by the image processing unit and store the processed image data in the memory as output image data of the target frame.

A method for applying facial masks to faces in live video. The method includes receiving an image containing a face from a user, wherein the image is a frame of a video and identifying the coordinates of a face in the image. The method also includes identifying the coordinates of facial elements within the face previously identified and synchronizing a bitmap add-on, wherein synchronizing the bitmap add-on includes aligning the bitmap add-on with the identified facial elements. The method further includes applying the bitmap add-ons over the frame of the identified face.

This disclosure is directed toward systems and methods of pre-multiplied alpha handling during image processing operations. The image processing circuitry may include hardware that enables removal and insertion of pre-multiplied alpha content into red, green, blue (RGB) pixel values during gamma and scaling operations. The division by alpha and multiplication by alpha hardware may enable removal of pre-multiplied alpha content to RGB pixel values prior to gamma operations and insertion of pre-multiplied alpha content into RGB pixel values prior to scaling operations.

This disclosure is directed toward systems and methods of pre-multiplied alpha handling during image processing operations. The image processing circuitry may include hardware that enables removal and insertion of pre-multiplied alpha content into red, green, blue (RGB) pixel values during gamma and scaling operations. The division by alpha and multiplication by alpha hardware may enable removal of pre-multiplied alpha content to RGB pixel values prior to gamma operations and insertion of pre-multiplied alpha content into RGB pixel values prior to scaling operations.

In one example, an apparatus comprises: a buffer memory; and a memory access circuit configured to: fetch, from a first memory, a set of first groups of data elements of a first matrix, each first group of data elements being stored at consecutive memory addresses at the first memory; based on a first configuration, store the set of first groups of data elements at consecutive memory addresses or at non-consecutive memory addresses at the buffer memory; based on a second configuration that defines a memory address offset, fetch a set of second groups of the data elements from the buffer memory, each second group of the data elements being stored at consecutive memory addresses of the buffer memory, each second group being separated by the memory address offset in the buffer memory; and store each fetched second group at consecutive addresses of a destination memory to form a second matrix.

In one example, an apparatus comprises: a buffer memory; and a memory access circuit configured to: fetch, from a first memory, a set of first groups of data elements of a first matrix, each first group of data elements being stored at consecutive memory addresses at the first memory; based on a first configuration, store the set of first groups of data elements at consecutive memory addresses or at non-consecutive memory addresses at the buffer memory; based on a second configuration that defines a memory address offset, fetch a set of second groups of the data elements from the buffer memory, each second group of the data elements being stored at consecutive memory addresses of the buffer memory, each second group being separated by the memory address offset in the buffer memory; and store each fetched second group at consecutive addresses of a destination memory to form a second matrix.

Systems, methods, and media for adjusting one or more images displayed to a viewer are provided. In some implementations, the system comprises: at least one processing circuit configured to: detect an orientation of a viewer based on at least two points associated with the viewer; determine, based on the orientation, a rotational position of a first image to be displayed on a display; and generate a display image for display on the display, wherein the display image includes at least a portion of the first image rotated based on the rotational position.

A method for applying facial masks to faces in live video. The method includes receiving an image containing a face from a user, wherein the image is a frame of a video and identifying the coordinates of a face in the image. The method also includes identifying the coordinates of facial elements within the face previously identified and synchronizing a bitmap add-on, wherein synchronizing the bitmap add-on includes aligning the bitmap add-on with the identified facial elements. The method further includes applying the bitmap add-ons over the frame of the identified face.

A method, system, and computer program product provide the ability to ink a drawing. A coarse original sketch is loaded. User input drawing an initial stroke over the coarse original sketch is accepted. A stroke smoothness of the initial stroke is measured. A similarity between the initial stroke and the coarse original sketch is measured to determine a snap affect. The stroke smoothness and the snap affect are combined. The initial stroke is automatically/dynamically, without additional user input, modified based on the combination.

An image processing apparatus includes a hardware processor that: divides each of pixels of image data in units of blocks, and compresses the image data using a maximum value and a minimum value of a pixel value in each of the divided blocks; extracts a maximum value and a minimum value of each of the blocks from the compressed image data; detects an edge of an object on the basis of at least one of the extracted maximum value and the minimum value of each of the blocks; performs edge correction of the compressed image data by increasing or decreasing the maximum value and the minimum value of each of the blocks within a correction range from the detected edge; and decompresses the image data that have undergone edge correction, using the maximum value and the minimum value of each of the blocks.