A display system is provided that comprises a display panel having a plurality of pixel arrangement. Each pixel arrangement comprises at least one light emitting unit, at least one driver circuit operably coupled to the light emitting unit, and at least one digital counter operably coupled to the driver circuit. In this regard, the digital counter is configured to store a data value to be counted and to toggle a state of the driver circuit upon expiry, thereby toggling a state of the light emitting unit to perform luminance control of the pixel arrangement.

A method of displaying an image in a display device may include determining the degree of deterioration of pixels included in a display unit based on image data of a current frame image, determining a shift route of the current frame image so as to correspond to the determined degree of deterioration. The first image data is corrected to second image data so that the current frame image is shifted along the shift route.

Local passive matrix displays and methods of operation are described. In an embodiment, the display includes a pixel driver chip coupled with a matrix of rows and columns of LEDs. The pixel driver chips may be arranged in rows across the display with separate portions to operate separate matrices of LEDs.

Methods and apparatuses relating to controlling an emission of a display panel. In one embodiment, a display driver hardware circuit includes row selection logic to select a number of rows in an emission group of a display panel, wherein the number of rows is adjustable from a single row to a full panel of the display panel, column selection logic to select a number of columns in the emission group of the display panel, wherein the number of columns is adjustable from a single column to the full panel of the display panel, and emission logic to select a number of pulses per data frame to be displayed, wherein the number of pulses per data frame is adjustable from one to a plurality and a pulse length is adjustable from a continuous duty cycle to a non-continuous duty cycle.

Addressing an emissive display having pixels arranged into rows and columns. A first clock signal is received at an address select input of a first row of the display. Data signals are received at data signal inputs of the first row of the display, each of the received data signals corresponding to a column of the display. When the first clock signal is active at the address select input, the data signals are output to corresponding drivers of light emitting semi-conductors of the first row and via corresponding data signal outputs of the first row. The data signals are received from the data signal outputs of the first row at a first row of shift registers. A second clock signal is received at the first row of shift registers. When the second clock signal is active, the data signals are output from the first row of shift registers.

A data transmission system comprises an operation apparatus and a matrix display apparatus. The matrix display apparatus includes a display panel and a control unit. The control unit receives a data stream and transmits at least a part of the data stream to an electrode on the display panel. When the operation apparatus operates on a display surface of the matrix display apparatus, at least a part of the data stream is coupled to the operation apparatus from the matrix display apparatus. Thereby, the data stream such as data or file can be transmitted to the operation apparatus from the matrix display apparatus through a wireless communication. The data transmission system of the invention can be combined with the application of the near field communication, and the data or file can be transmitted to another electronic apparatus through the display apparatus so that the application can be expanded.

A display system includes a display panel having an input to receive pixel data, the pixel data comprising a plurality of pixel values, an array of pixels partitioned into a foveal region and at least one peripheral region, and an array controller to group pixels in the at least one peripheral region into subsets of at least two pixels and to control each subset using a corresponding single pixel value from the plurality of pixel values. The display system further may include a rendering system to foveally render a display image based on the locations of the foveal region and the at least one peripheral regions, wherein for each row of the display image having pixels within at least one of the peripheral region, a number of pixel values represented in the pixel data for the row is less than a number of pixels in the row.

To provide an active matrix display device in which power consumption of a signal line driver circuit can be suppressed, so that power consumption of the entire memory can be suppressed. A plurality of memory circuits which can write data of a video signal input to a pixel in one line period and can hold the data are provided in a signal line driver circuit of a display device. Then, the data held in each memory circuit is input to a pixel of a corresponding line as a video signal. By providing two or more memory circuits in a driver circuit, pieces of data of video signals corresponding to two or more line periods can be concurrently held in the memory circuits.

Embodiments relate to a signal detector circuit suitable for a display device that detects and decodes a power line communication signal. The signal detector circuit includes an averaging circuit, a comparator, a sampling circuit, a decoder circuit, and a regulator circuit. The averaging circuit receives the power line communication signal and averages the power line communication signal over time to generate an average signal. The comparator compares the average signal to the power line communication signal and generates a comparison signal. The sampling circuit samples the comparison signal according to a sample timing of a clock signal and generates a sampled signal. The decoder circuit decodes the sampled signal and generates a decoded output signal. The regulator circuit receives the power line communication signal and generates supply voltage to power the comparator, the sampling circuit, and the decoder circuit.

A method of calculating a hologram having an amplitude and a phase component. The method comprises (i) receiving an input image comprising a plurality of data values representing amplitude. The method then comprises (ii) assigning a random phase value to each data value of the plurality of data values to form a complex data set. The method then comprises (iii) performing an inverse Fourier transform of the complex data set. The method then comprises (iv) constraining each complex data value (X1, X2) of the transformed complex data set to one of a plurality of allowable complex data values (GL1-GL8), each comprising an amplitude modulation value and a phase modulation value, to form a hologram, wherein, the phase modulation values (GL1-GL7) of the plurality of allowable complex data values substantially span at least 3π/2 and at least one of the allowable complex data values has an amplitude modulation value of substantially zero (GL8) and a phase modulation value of substantially zero.