A display device, includes: a scan driver configured to sequentially supply scan signals having a turn-on level to the first scan line and the second scan line during a first period and to concurrently supply scan signals having a turn-on level to the first scan line and the second scan line during a second period after the first period, wherein: a mask period corresponds to a difference between a start point of the second period and a start point of the first period in a next frame period, a first frame period and a second frame period have different mask periods, a third frame period between the first frame period and the second frame period has a same mask period as the first frame period, and a fourth frame period between the first frame period and the second frame period has a same mask period as the second frame period.

A display panel is provided. The display panel includes at least one transistor of a split structure. The transistor of the split structure comprises a control electrode, a first electrode and a second electrode; the first electrode comprises N first electrode portions, the second electrode comprises N second electrode portions, and N is an integer greater than 2; the N first electrode portions are electrically coupled, and the N second electrode portions are electrically coupled; the display panel has a plurality of transistor regions arranged at intervals, an n-th first electrode portion and an n-th second electrode portion are located in a same transistor region, an m-th first electrode portion and an (m+1)-th first electrode portion are respectively located in two adjacent transistor regions, n and in are an positive integers, n is less than or equal to N, and in is less than or equal to N−1.

A driving method for a backlight module and a display device are disclosed. The driving method includes: generating mapping information from each local dimming area to the corresponding piece of local area dimming data according to preset positional relationships between a backlight driving chip and lamp beads in the backlight module; receiving, by a timing control chip, a frame of display data, and converting the display data into panel driving data and corresponding multiple pieces of local area dimming data; receiving, by a backlight driving circuit, the multiple pieces of local area dimming data in sequence, turning on the channel corresponding to the current local dimming area in turn according to the mapping information, and driving the lamp beads in the current local dimming area.

A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.

A power circuit according to the present disclosure may include a multiplexer connected to a first power line and a second power line and selecting and outputting one of a first voltage supplied through the first power line and a second voltage supplied through the second power line. Further, the power circuit may include a first power circuit which generates a first driving voltage and a second driving voltage by using a voltage supplied from the multiplexer, recognizes whether there is the first voltage supplied through the first power line, and does not output the first driving voltage when the first voltage is not recognized.

A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

An electronic device is provided. The electronic device includes a housing comprising a front plate facing a first direction, a rear plate facing a second direction opposite to the first direction, and a side member configured to enclose a space between the front plate and the rear plate, a display panel having a first surface viewed through the front plate, a cover panel coupled to a second surface of the display panel and positioned at an inner area of the display panel, the cover panel comprising a hole formed adjacent to a first edge of the display panel, and a sensor comprising a light receiving portion positioned to correspond to a position of the hole of the cover panel, and a light emitting portion positioned at an outer area of the display panel.

A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.