A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

An electronic device, an electronic system, and a control method are provided. The electronic device includes a display, a memory, and a processor. The memory stores an audiovisual module and a control module. The processor receives initial image information from an external electronic device through a bridge device. The processor is coupled to the display and the memory. The processor executes the audiovisual module to transform the initial image information with a first image format into transformed image information with a second image format, which is compatible to the display. The processor controls the display to display according to the transformed image information. The processor executes the control module to receive a control signal for operating the transformed image information, and provide the control signal to the external electronic device through the bridge device.

A display driver circuit configured to drive a display panel includes a memory, a decoder, and a controller. The memory stores first data using data from outside of the display driver circuit. The decoder decodes the stored first data. The controller generates compression data using the decoded first data. While an image based on the decoded first data is displayed on the display panel, when second data based on the data from the outside are not stored in the memory after the first data are stored in the memory, the controller controls the decoder such that the decoder does not operate and controls the memory such that the compression data are stored in the memory.

The present disclosure provides a shift register unit, a signal generation unit circuit, a driving method and a display device. The shift register unit includes a first node control circuit, a second node control circuit and an output circuit, the first node control circuit is used to control a potential of a first node; the second node control circuit controls a potential of a second node; the output circuit is used to control and maintain the potential of the first node and the potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the input terminal and the second voltage terminal under the control of the potential of the second node.

There is provided an information processing device including a voltage detection unit configured to monitor a voltage value of a signal output at a predetermined timing, and a signal control unit configured to stop output of the signal if the voltage value after a predetermined time elapses from when the voltage value detected by the voltage detection unit exceeds a first value does not exceed a second value greater than the first value.

A display presents picture-in-picture and/or picture-by-picture formatted visual information initiated by secondary information handling systems while the display presents primary visual information. The display broadcasts plural partial video buffer definitions to plural information handling systems that can selectively initiate network sessions to present visual images in areas of the display by storage of visual image information in a portion of the display video buffer. The secondary display area may present visual images for IoT or similar headless devices having relevance to an end user of a primary information handling system.

Systems and methods for displaying super saturated color. Image data for display on a display or viewing device with a potential white luminance in a standard system with a maximum luminance is processed such that colors near the white point are reduced to a limited luminance. As the chroma of the displayed color is increased, a luminance attenuation is decreased. The scaling of the reduction is operable to be a linear function, a non-linear function, or any other function.

A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.

This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.

Systems and methods for a multi-primary color system for display. A multi-primary color system increases the number of primary colors available in a color system and color system equipment. Increasing the number of primary colors reduces metameric errors from viewer to viewer. One embodiment of the multi-primary color system includes Red, Green, Blue, Cyan, Yellow, and Magenta primaries. The systems of the present invention maintain compatibility with existing color systems and equipment and provide systems for backwards compatibility with older color systems.