Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

In an embodiment, a user equipment (UE) coupled to a display screen enters into a reduced blue light (RBL) mode. The UE determines, while operating in accordance with the RBL mode, a degree of blue light reduction in at least a portion of a display frame to be output on the display screen using at least one RBL rule from a set of RBL rules that is based upon one or more of (i) application-specific information of an application that is contributing image data to the portion of the display frame, and (ii) content-specific information that characterizes the image data in the portion of the display frame. The UE selectively reduces the blue light in the at least a portion of the display frame based on the determining. The UE sends the display frame with the selectively reduced blue light portion to the display screen for output.

Embodiments of the present disclosure include apparatuses and method for a stacked light emitting diode (LED) hologram display. A stacked LED hologram display can include a first array of LEDs that are configured to emit red light received by a meta-optics panel configured to display a first portion of a holographic image, a second array of LEDs that are configured to emit green light received by a meta-optics panel configured to display a second portion of a holographic image, and a third array of LEDs that are configured to emit blue light received by a meta-optics panel configured to display a third portion of a holographic image. The stacked LED hologram display can include a number of actuators configured to adjust a position of a first array of LEDs in first direction and a second direction, adjust a position of a second array of LEDs in the first direction and the second direction, and adjust a position of a third array of LEDs in the first direction and the second direction.

A method, device and non-transitory computer-readable storage medium for controlling a frame rate of a mobile terminal are disclosed. The method includes obtaining a rendering frame rate of a target object in a current running scene, the target object including a target application or a target layer, setting a composition frame rate in the current running scene according to the rendering frame rate of the target object, composing rendered images in the current running scene at the composition frame rate, and displaying a composed image.

A method for optical calibration of a plurality of displays is provided. At a manufacturing stage, a plurality of one-time programmable (OTP) values for each display is created, each OTP value including a value of manufacture gamma voltage corresponding to a manufacture luminance and color value. The OTP values are stored in non-volatile memory of the respective display. At an assembly stage, each display is connected to a respective power management integrated circuit (PMIC); assembly test voltages are applied corresponding to the manufacture gamma voltage of each stored OTP value. Differences between assembly luminance and color values of each display and an expected value as a result of applying each assembly test voltage are measured. For each display, one value of manufacture gamma voltage of a respective OTP value is selected that corresponds to a minimal difference between the assembly luminance and color values and the expected value.

A three-dimensional (3-D) look up table (LUT) can be accessed using an address decoder to identify a plurality of vertices in the 3-D LUT based on a number (m) of most significant bits (MSBs) of three coordinate values representative of a first color and a non-zero integer (p). The three coordinate values are determined by a source gamut. One or more memories store component values representative of a plurality of second colors determined by a destination gamut. The component values are stored at memory locations associated with the plurality of vertices. An interpolator maps the input color to an output color in the destination gamut based on the component values.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

A display device (10) includes: an integrated control unit (31) that allows selection from among at least a high-luminance mode and a luminance-unevenness-suppression-preferred mode in accordance with an input instruction; and an unevenness correction unit (36) that performs color unevenness correction for each pixel in both the high-luminance mode and the luminance-unevenness-suppression-preferred mode. In the luminance-unevenness-suppression-preferred mode, the unevenness correction unit (36) performs a pixel value limitation process for uniformly shifting, for each pixel, a pixel value in image data to a lower pixel value to thereby decrease the pixel value to a pixel value lower than that in the high-luminance mode, and thereafter, performs the color unevenness correction. Accordingly, even if the use of the display device varies, image processing that is appropriate for various uses is implemented.

An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.