A method for optical calibration of a plurality of displays is provided. At a manufacturing stage, a plurality of one-time programmable (OTP) values for each display is created, each OTP value including a value of manufacture gamma voltage corresponding to a manufacture luminance and color value. The OTP values are stored in non-volatile memory of the respective display. At an assembly stage, each display is connected to a respective power management integrated circuit (PMIC); assembly test voltages are applied corresponding to the manufacture gamma voltage of each stored OTP value. Differences between assembly luminance and color values of each display and an expected value as a result of applying each assembly test voltage are measured. For each display, one value of manufacture gamma voltage of a respective OTP value is selected that corresponds to a minimal difference between the assembly luminance and color values and the expected value.

A display controller provides an output frame to a display for display by sending respective output surface regions that together form the output frame, each respective region of the output surface being generated from a respective region or regions of one or more input surfaces, to the display. When a new version of an output surface region is generated, the display controller determines whether the output surface region has been unchanged for a period, and if it has, then stores the generated output surface region in a frame buffer. Then, for the subsequent frame, checks are performed to see if the output surface region could have changed. If there is no change the stored version of the output surface region is reused, but if there is a change in the output surface region, the output surface region is regenerated.

A method and apparatus are provided for generating image data for output to a display device such as an HUD or HMD defining pixels of an image for display. The image data for each pixel defines a predetermined background colour or a non-background colour. In an example implementation, the image generator comprises at least one image rendering module and a memory accessible by the at least one rendering module providing at least one frame buffer in which image data may be assembled. The at least one rendering module is arranged to process or to generate image data using a tile representation of an image for display, each tile comprising image data defining each of a predetermined number of pixels of the image. Furthermore, the at least one rendering module is arranged to store image data for the pixels of a tile in the at least one frame buffer only in the event that one or more pixels of the tile have respective image data defining a non-background colour or are enabled for display with a non-background colour, the pixels in the tile being otherwise assumed to be intended for display with the predetermined background colour. In this way the need to transfer data to and from the memory when generating and assembling image data is reduced, so reducing image rendering time.

A storage system comprising storage including a plurality of storage banks and a storage controller to control writing of received pixel data to the storage banks in a distribution pattern. The distribution pattern includes pattern sections, each of which corresponds to pixels from a row of input pixels, and pattern blocks, each of which corresponds to pixels from a plurality of adjacent rows and columns of the input pixels. Pixel data in a pattern section and a pattern block are each written to different ones of the storage banks. The pattern section includes a first section part, which overlaps the pattern block and a second section part, which does not overlap the pattern block. Pixel data of the first section part is written to a first set of storage banks and pixel data of the second section part is written to a second, different, set of storage banks.

A controller includes a frame memory configured to store an image frame, a frame memory controller coupled to the frame memory and configured to obtain image data from the image frame. The image data is associated with a color component of the image frame. The controller also includes a dither noise mask generator configured to provide dither noise masks according to dither noise levels for the image data, and a bit plane generator coupled to the frame memory controller and the dither noise mask generator and configured to generate bit planes based on the dither noise masks for the image data.

Embodiments of the present disclosure include apparatuses and method for a stacked light emitting diode (LED) hologram display. A stacked LED hologram display can include a first array of LEDs that are configured to emit red light received by a meta-optics panel configured to display a first portion of a holographic image, a second array of LEDs that are configured to emit green light received by a meta-optics panel configured to display a second portion of a holographic image, and a third array of LEDs that are configured to emit blue light received by a meta-optics panel configured to display a third portion of a holographic image. The stacked LED hologram display can include a number of actuators configured to adjust a position of a first array of LEDs in first direction and a second direction, adjust a position of a second array of LEDs in the first direction and the second direction, and adjust a position of a third array of LEDs in the first direction and the second direction.

A layered content display system includes a networking device coupled to a network, a source device configured to display first content information on a source device screen, a display device, and a sink device coupled to the networking device, the source device, and the display device. The sink device receives an identification of the first content information from the source device. The sink device then retrieves a first subset of the first content information from the source device, and a second subset of the first content information from the network through the networking device. The sink device then provides the second subset of the first content information layered with the first subset of the first content information for display on the display device such that the first content information displayed on the display device is substantially similar to the first content information displayed on the source device screen.

While reducing memory usage, page related data is made available. Data obtaining means of an electronic book display device obtains electronic book data including a plurality of pages stored in storing means for storing the electronic book data. Display controlling means displays, on display means, one or more pages specified in the plurality of pages based on the electronic book data obtained by the data obtaining means. Page related data generating means generates, before the display means displays at least one of preceding and succeeding pages to the one or more pages displayed on the display means, page related data based on the at least one of the pages and writes the generated page related data in the storing means.

An information processor includes: a communication section, a reception section, a communication control section, a storage section, and a storage control section. The communication section transmits/receives data to/from an external server. The reception section receives instructions from a user. The communication control section controls data communication operation performed by the communication section and causes the communication section to receive, from the server, data which is included in a plurality of pieces of data stored in the server and which is specified by the instruction received by the reception section. The storage control section causes the storage section to store the data received from the server by the communication section. In a case where the data received by the communication section is the data received from a predefined server, the data is deleted from the storage section when predefined time has passed since predefined processing was performed on the data.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.