Data structures, methods and primitive block generators for storing primitives in a graphics processing system. The method includes: receiving a primitive associated with state data that defines how the primitive is to be rendered; determining whether the state data associated with the received primitive matches state data for a current primitive block; and in response to determining that the state data for the received primitive matches the state data for the current primitive block: determining, based on one or more primitive section size constraints, whether the received primitive is to be added to a current primitive section of the current primitive block in a data store; in response to determining that the received primitive is to be added to the current primitive section, adding the received primitive to the current primitive section; and in response to determining that the received primitive is not to be added to the current primitive section: outputting the current primitive section; reconfiguring the data store to store a new primitive section for the current primitive block; and adding the received primitive to the new primitive section for the current primitive block.

Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

A caption encoder system is provided that can include a computer system and a caption encoder card. The caption encoder card can include a caption encoder module having at least one of: an input component, a field programmable gate array (FPGA), a microcontroller unit (MCU), a peripheral component interconnect express (PCIe) bridge, and a plurality of output components. The input component can be configured to receive an input SDI stream. The FPGA can be in communication with the input component and can be configured to compile an output SDI stream with embedded closed captions. The MCU can be in communication with the FPGA. The PCIe bridge can be in communication with the microcontroller unit and a plurality of universal serial bus to serial devices. The plurality of output components can be communication with the field programmable gate array.

In some examples, a method includes receiving, by a timing controller of a display device, an indication from an embedded controller of a computing device during a computing device startup procedure. In some examples, the method includes determining, by the timing controller, whether to access display image memory or computing device image memory based on the indication. In some examples, the method includes accessing, by the display device, the computing device image memory in response to determining to access the computing device image memory. In some examples, the method includes causing the display device to display an image from the computing device image memory in response to determining to access the computing device image memory.

The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process at least one frame including frame content associated with a grid including a plurality of grid sections, each of a plurality of portions of the frame content being aligned with at least a portion of at least one of the plurality of grid sections. The apparatus may also shift the frame content with respect to the grid, such that at least one portion of the plurality of portions of the frame content is aligned with at least a portion of at least one distinct grid section of the plurality of grid sections. Additionally, the apparatus may store the shifted frame content including the at least one portion of the frame content that is aligned with at least a portion of the at least one distinct grid section.

A display device can include a display panel including a plurality of subpixels configured to display an image; a data driving circuit configured to supply a data signal to the plurality of subpixels; a gate driving circuit configured to supply a gate signal to the plurality of subpixels; and a timing controller configured to receive image data of a subsequent frame of an image of a current frame being displayed on the display panel, and differently control the data driving circuit during a blank period between the current frame and the subsequent frame based on a gray value of at least one edge subpixel among a plurality of edge subpixels in the image data of the subsequent frame. the plurality of edge subpixels are subpixels among the plurality of subpixels that are located adjacent to the gate driving circuit or at an edge of the display panel.

Apparatuses, systems, and techniques are presented to reduce temporal lag when a dynamic event is occurring in computer generated video. In one embodiment, a first averaging algorithm is utilized to determine a display value for a pixel based at least in part on previous pixel values. Once a dynamic event is detected, a set of the previous pixel values is averaged using a second averaging algorithm. The pixel value is updated based on the first averaging of the pixel values and the second averaging of the pixel values to determine a current pixel value.

A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.

A video processing system (100) comprises at least one controller (102) configured to receive a plurality of video data from a respective plurality of video data sources (106, 208). The system can assign one of a plurality of hierarchical display layers to each of the plurality of video data, and generate an output video for display, the output video comprising at least a portion of each of the plurality of video data layered according to the assigned hierarchical display layers. The plurality of hierarchical display layers is based on a respective plurality of safety/security levels defined in a safety/security standard.

Methods and systems are disclosed for creating a computerized 3D model to include material property information for one or more regions of image textures of the computerized 3D model, including a method comprising: creating a computerized 3D model having image textures; examining a portion of a first image texture of the computerized 3D model having unknown material properties; assigning a material having a material property to the portion of the first image texture to indicate a physical material of a physical object represented by the portion of the first image texture, the material property having material property information about the physical materials; associating the material property information with the portion of the first image texture; and replacing the portion of the first image texture in the 3D model with a simulated texture of the assigned material.