Techniques and mechanisms for changing a consistency with which a cell circuit (cell) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCl) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCl stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Methods and systems for compensating a display of an electronic device using internal sensing and external compensation. The external compensation uses a generated compensation map that then is used to compensate for variations that occur outside of display circuitry. The internal sensing compensation is used to compensate for internally sensed parameters (e.g., aging) of the display.

Methods and systems for compensating a display of an electronic device using internal sensing and external compensation. The external compensation uses a generated compensation map that then is used to compensate for variations that occur outside of display circuitry. The internal sensing compensation is used to compensate for internally sensed parameters (e.g., aging) of the display.

Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.

Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.

A display driver includes a processing circuit that performs gray level gamma conversion processing on display data, a memory that stores correspondence information, and a drive circuit. The memory stores lower n bits of m-bit output gray level data in an output gray level group, the processing circuit generates output gray level data corresponding to the m-bit input gray level data based on lower n-bit data, and the drive circuit outputs a drive voltage based on the output gray level data.

A display driver includes a processing circuit that performs gray level gamma conversion processing on display data, a memory that stores correspondence information, and a drive circuit. The memory stores lower n bits of m-bit output gray level data in an output gray level group, the processing circuit generates output gray level data corresponding to the m-bit input gray level data based on lower n-bit data, and the drive circuit outputs a drive voltage based on the output gray level data.

Various methods and apparatus for graphics processing are disclosed. In one aspect, a method of graphics processing using a computing system is provided. The method includes booting the computing system. After booting the computing system operating video memory of the computing system at a non-overclocked frequency, and prior to rebooting having the computing system sequentially increment the frequency of video memory by a selected change in frequency through a series of overclocked frequencies, after each frequency incrementing writing data to the video memory and testing the stability of the video memory data writing, and if the stability testing fails then decrementing the frequency of the video memory to a previous overclocked frequency at which the stability testing did not fail.

Systems and methods for improving perceived image quality with reduced implementation associated cost and/or improved operational efficiency. A display pipeline includes an input buffer that stores input image data corresponding with an image pixel window, in which the input image data has a first bit-depth and includes image data corresponding with an image pixel in the image pixel window. The display pipeline includes bit-depth adjustment circuitry, which includes a neural network that operates based on a set of bit-depth adjustment parameters to process the input image data to determine whether banding greater than a perceivability threshold is expected to result when the image is displayed directly using the input image data with the first bit-depth and to process the image data corresponding with the image pixel to expand the image data from the first bit-depth to a second bit-depth when the banding visual artifact is greater than the perceivability threshold.

Systems and methods for improving perceived image quality with reduced implementation associated cost and/or improved operational efficiency. A display pipeline includes an input buffer that stores input image data corresponding with an image pixel window, in which the input image data has a first bit-depth and includes image data corresponding with an image pixel in the image pixel window. The display pipeline includes bit-depth adjustment circuitry, which includes a neural network that operates based on a set of bit-depth adjustment parameters to process the input image data to determine whether banding greater than a perceivability threshold is expected to result when the image is displayed directly using the input image data with the first bit-depth and to process the image data corresponding with the image pixel to expand the image data from the first bit-depth to a second bit-depth when the banding visual artifact is greater than the perceivability threshold.