A display apparatus includes a base substrate that includes a display area in which pixels are formed and a peripheral area that is a non-display area that surrounds the display area, a first conductive pattern layer disposed on the base substrate, a first insulating layer disposed on the first conductive pattern layer, a second conductive pattern layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive pattern layer, and a third conductive pattern layer disposed on the second insulating layer. The peripheral area includes a first wiring area and a circuit area.

A TFT array panel includes a primary display area and a slitting-edge display area. In the slitting-edge display area, a first metallic routing layer includes a first data line and a second metallic routing layer includes a first gate line. The first data line is connected to the second metallic routing layer through a hole in the interlayer dielectric layer so that the first data line overlaps the first gate line to form an overlapping capacitance to compensate for a gate line RC value.

The embodiments of the present disclosure provide a gate driving circuit and its driving method, an array substrate and a display device. The gate driving circuit is configured to drive an irregular-shaped display panel that includes a regular-shaped display area and a first irregular-shaped display area, wherein the gate driving circuit includes a first driving module configured to drive one or more first scan lines in the regular-shaped display area and a second driving module configured to drive one or more second scan lines in the regular-shaped display area; wherein one or more third scan lines are driven by the first driving module or the second driving module, and one or more fourth scan lines are driven by the first driving module or the second driving module.

A display device according to an exemplary embodiment of the invention includes: a substrate; an active pattern including a semiconductor material disposed on the substrate; a first conductive layer disposed on the active pattern, the first conductive layer including a plurality of scan lines and a driving gate electrode; a second conductive layer disposed on the first conductive layer, the second conductive layer including an initialization voltage line to transmit an initialization voltage; a third conductive layer disposed on the second conductive layer, the third conductive layer including a driving voltage line to transmit a driving voltage; a fourth conductive layer disposed on the third conductive layer, the first conductive layer including a first data line that transmits a data signal; and a pixel electrode layer disposed on the fourth conductive layer, the pixel electrode layer including a plurality of pixel electrodes, wherein the third conductive layer includes a connection member that is electrically connected with the initialization voltage line, and the first data line includes a projecting portion that extends in a direction away from the connection member.

A display device and a three-dimensional display method therefor, wherein a display panel is internally provided with sub-pixels and black matrices that are alternately arranged, and in each two adjacent columns of sub-pixels, sides of each sub-pixel and black matrix connected in the column direction are aligned in the same longitudinal straight line. In a three-dimensional display mode, at least every two columns of sub-pixels are a view area, and adjacent view areas are used for providing gray-scale information of different view images; and in the three-dimensional display mode, a three-dimensional grating forms light-transmitting areas and light-blocking areas that are alternately arranged in the row direction

A driving circuit, an array substrate and a display device are provided. The driving circuit includes a plurality of cascaded shift registers. Each shift register includes a plurality of transistors and at least one capacitor, and a channel width-to-length ratio of at least one transistor is determined by a preset number of pixels in a pixel row driven by the corresponding shift register.

An EL display apparatus is provided. A display screen includes pixels arranged in a matrix, with each pixel including an EL device and a pixel circuit. A source driver circuit is configured to output an analog video signal to each pixel. A gate driver circuit is on at least one side of the display screen, with the gate driver circuit including first and second gate driver circuits. Each pixel includes a driving transistor, a first switch transistor, and a second switch transistor. A gate terminal of the first switch transistor is connected to a first gate signal line of the first gate driver circuit, and a gate terminal of the second switch transistor is connected to a second gate signal line of the second gate driver circuit. The first and second switch transistors are on/off controlled, independently, by the first and second gate driver circuits.

A display device includes a display panel including scan lines, data lines, and a plurality of pixels coupled to the scan lines and the data lines, a voltage generator configured to generate an on-voltage and an off-voltage, a scan controller configured to generate a scan start signal based on the on-voltage, the off-voltage, and a vertical start signal, and a scan driver configured to generate a scan signal based on the scan start signal and to provide the scan signal to a scan line of the scan lines. The scan controller is configured to detect a voltage level of the scan start signal and to output a shutdown signal based on the voltage level of the scan start signal during an over current detecting period.

An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region, and a power source circuit configured to supply power source voltages at a plurality of levels to the demultiplexer circuit. The demultiplexer circuit includes a boost circuit configured to increase a voltage to be applied to a gate electrode of a switching TFT. The boost circuit includes a set up unit to be driven by a first drive signal to pre-charge a node coupled to the gate electrode, a reset unit to be driven by a second drive signal to reset a potential of the node, and a boost unit to be driven by a third drive signal to increase the potential of the node pre-charged by the set up unit. An amplitude of the first drive signal and an amplitude of the second drive signal are identical to each other. An amplitude of the third drive signal differs from the amplitudes of the first drive signal and the second drive signal.

A field-effect transistor including: a gate electrode, which is configured to apply gate voltage; a source electrode and a drain electrode, which are configured to take electric current out; an active layer, which is disposed to be adjacent to the source electrode and the drain electrode and is formed of an oxide semiconductor; and a gate insulating layer, which is disposed between the gate electrode and the active layer, wherein the gate insulating layer contains a paraelectric amorphous oxide containing a Group A element which is an alkaline earth metal and a Group B element which is at least one selected from the group consisting of Ga, Sc, Y, and lanthanoid, and wherein the active layer has a carrier density of 4.010.sup.17/cm.sup.3 or more.