A light emitting assembly includes active matrix (AM) light emitting circuits and an AM driver circuit. Each AM light emitting circuit includes at least one light emitting element, at least one shift register and a current control sub-circuit. The at least one shift register is configured to generate a control signal according to the clock signal from a clock line and the data signal from an inter-array data line and the control signal from the at least one shift register. The current control sub-circuit is configured to control the brightness of the at least one light emitting element according to the base current from a current supply line and the control signal. The AM driver circuit is configured to generate the data signal according to a serial data packet, and provide the data signal, the clock signal and the base current to the AM light emitting circuits.

A flat-panel display comprises an array of pixels distributed in rows and columns. A first wire segment is electrically connected to a first subset of pixels in a row or column of pixels that conducts a signal between a controller and the first subset of pixels, and a second wire segment is electrically connected to a second subset of pixels in the row or column of pixels. A signal regeneration circuit electrically connected to the first wire segment and to the second wire segment regenerates a signal conducted on the first wire segment and drives the regenerated signal onto the second wire segment or regenerates a signal conducted on the second wire segment and drives the regenerated signal onto the first wire segment.

A light emitting assembly includes active matrix (AM) light emitting circuits and an AM driver circuit. Each AM light emitting circuit includes at least one light emitting element, at least one shift register and a current control sub-circuit. The at least one shift register is configured to generate a control signal according to the clock signal from a clock line and the data signal from an inter-array data line and the control signal from the at least one shift register. The current control sub-circuit is configured to control the brightness of the at least one light emitting element according to the base current from a current supply line and the control signal. The AM driver circuit is configured to generate the data signal according to a serial data packet, and provide the data signal, the clock signal and the base current to the AM light emitting circuits.

Apparatus, methods, and articles of manufacture for a micro-LED display are disclosed. An example apparatus for a micro-LED display includes a substrate, a micro-LED matrix on a first side of the substrate, a driver circuit on a second side of the substrate, the second side opposite the first side, and a conductive path in the substrate to extend between the first side and the second side to electrically couple the micro-LED matrix to the driver circuit.

A display driving integrated circuit includes a common voltage buffer configured to provide a common voltage to a display panel and when a line outputting the common voltage and a gate line are short-circuited, apply a first current to the gate line or receive a second current from the gate line; a current generator configured to sum currents respectively corresponding to the first current and the second current and output an output current obtained by the summing; and a current detector configured to convert the output current into an output voltage and output a high or low signal based on a result of comparing the output voltage with a preset voltage.

Provided is a display panel and a display apparatus, the display panel includes a first display area including a plurality of first light-emitting devices and a plurality of first pixel driving circuits; and a light-transmitting display area including a plurality of second light-emitting devices and a plurality of second pixel driving circuits. Each of the plurality of light-emitting devices is electrically connected to one of the plurality of first pixel driving circuits. Each of the second light-emitting devices is electrically connected to one of the plurality of second pixel driving circuits. The second pixel driving circuits electrically connected to the second light-emitting devices in at least two columns are located in the same column. The second pixel driving circuits located in the same column and connected to the second light-emitting devices in different columns are respectively connected to different data signal wires.

A timing control board includes a point-to-point interface, a storage, a signal input port and a timing controller. The storage is for storing multiple sets of different point-to-point configuration parameters. The timing controller obtains a set of point-to-point configuration parameters matching a protocol type of a source drive circuit board in the storage according to the configuration parameter selection signal, and initializes settings according to the set of point-to-point configuration parameters to generate matched data signals and output the data signals to the source drive circuit board through the point-to-point interface, so as to realize the compatibility of display panels and reduce the design cost.

An EL display apparatus is provided. A display screen includes pixels arranged in a matrix, with each pixel including an EL device and a pixel circuit. A source driver circuit is configured to output an analog video signal to each pixel. A gate driver circuit is on at least one side of the display screen, with the gate driver circuit including first and second gate driver circuits. Each pixel includes a driving transistor, a first switch transistor, and a second switch transistor. A gate terminal of the first switch transistor is connected to a first gate signal line of the first gate driver circuit, and a gate terminal of the second switch transistor is connected to a second gate signal line of the second gate driver circuit. The first and second switch transistors are on/off controlled, independently, by the first and second gate driver circuits.

To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

A wire component includes a plurality of working signal lines and a plurality of transmitting lines. The working signal lines are configured to respectively provide a plurality of working signals to a driving circuit, and phases of the working signals at least partially lag each other sequentially. The transmitting lines are configured to respectively transmit the working signals, and a portion of the transmitting lines crosses the working signal lines. A first working signal line is configured to provide a first working signal; a second working signal line is configured to provide a second working signal; the first working signal immediately lags the second working signal, and the first working signal line and the second working signal line are arranged with another working signal line therebetween.