Provided is an active matrix substrate (100) that includes multiple pixel TFTs (10), multiple gate wiring lines (GL) along which a scanning signal is supplied to the multiple pixel TFTs, multiple source wiring lines (SL) along which a display signal is supplied to the multiple pixel TFTs, a gate driver (20) that drives multiple gate wiring lines, and a source driver (30) that drives multiple source wiring lines. At least one of the gate driver and the source driver includes a current mirror circuit (70). The current mirror circuit is configured with two oxide semiconductor TFTs (71c and 72c) each of which includes an oxide semiconductor layer.

A display device includes a substrate which includes a display area and a non-display area, a pixel unit which is provided in the display area and includes a plurality of pixel columns, and data lines which are respectively connected to the pixel columns and apply data signals to the pixel columns. The non-display area includes a fanout area, a bent area, and a pad area which are sequentially arranged. The respective data lines are disposed on different layers in the fanout area and the pad area. A resulting display device can reduce resistance deviation between data signals in a first data line and a second data line, thereby reducing vertical line defects.

To provide a display device having a small circuit area and low power consumption. The display device includes a semiconductor device and a D/A converter circuit, and the semiconductor device includes first to third transistors and first and second capacitors. A first terminal of the first transistor is electrically connected to a first terminal of the first capacitor. A first terminal of the second transistor is electrically connected to a gate of the third transistor, a second terminal of the first capacitor, and a first terminal of the second capacitor. A first terminal of the third transistor is electrically connected to a second terminal of the second capacitor. An output terminal of the D/A converter circuit is electrically connected to a second terminal of the first transistor and a second terminal of the second transistor. Supply of a potential to the first terminal of the first capacitor changes (finely adjusts) the potential of the gate of the third transistor to be more precise than a potential that can be output from the D/A converter circuit.

To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

A wire component includes a plurality of working signal lines and a plurality of transmitting lines. The working signal lines are configured to respectively provide a plurality of working signals to a driving circuit, and phases of the working signals at least partially lag each other sequentially. The transmitting lines are configured to respectively transmit the working signals, and a portion of the transmitting lines crosses the working signal lines. A first working signal line is configured to provide a first working signal; a second working signal line is configured to provide a second working signal; the first working signal immediately lags the second working signal, and the first working signal line and the second working signal line are arranged with another working signal line therebetween.

To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

An active matrix substrate includes a demultiplexer circuit arranged in a peripheral region. Each unit circuit in the demultiplexer circuit includes n switching TFTs. The demultiplexer circuit includes a boost circuit capable of boosting a voltage applied to a gate electrode of the switching TFT. The boost circuit includes a set unit configured to perform a set action, a boost unit configured to perform a boost action, and a reset unit configured to perform a reset action. The set unit includes a setting TFT including a drain electrode connected to the drive signal line and a source electrode connected to a node connected to the gate electrode of the switching TFT. When the set unit performs the set action, a first signal voltage is supplied from the drive signal line to the drain electrode of the setting TFT, and a second signal voltage higher than the first signal voltage is supplied to the gate electrode of the setting TFT.

Provided are a transfer substrate, a display panel and a transfer method. The transfer substrate includes a plurality of object setting regions arranged in an array, the plurality of object setting regions including n types, where n is a positive integer, and n2. The transfer substrate further includes: a base substrate, and a blocking layer located on a side of the base substrate. The blocking layer forms accommodating grooves respectively within object setting regions. Phase change materials are provided in accommodating grooves of at least (n1) types of object setting regions. The provided transfer substrate has a simple structure and high transfer efficiency.

Provided is a display panel and a display apparatus, the display panel includes a regular display area including first pixel units and first pixel driving circuits, and a light-transmitting display area including second pixel units and second pixel driving circuits; the first pixel units include first light-emitting devices electrically connected to the first pixel driving circuits; the second pixel units have smaller density than the first pixel units, and the second pixel units in adjacent rows are arranged in a staggered manner; the second pixel unit includes second light-emitting devices electrically connected to the second pixel driving circuits; the second pixel driving circuits electrically connected to the second light-emitting devices in at least two columns are located in the same column, and the second pixel driving circuits in the same column and connected to the second light-emitting devices in different columns are respectively connected to different data signal wires.

Herein disclosed an image display including: row scan lines configured to supply a control signal; column signal lines configured to supply a video signal; and pixel circuits configured to be disposed at intersections between the scan lines and the signal lines, wherein each of the pixel circuits has at least a drive transistor, a sampling transistor connected to a gate of the drive transistor, a capacitive part connected between the gate and a source of the drive transistor, and a light-emitting element connected to the source of the drive transistor.