The present disclosure provides a display panel, including a substrate, a pixel driving circuit, a planarization layer, and a display area. The planarization layer is arranged on a side of the pixel driving circuit away from the substrate. The planarization layer includes a first area and a second area. The first area and the second area are in a direction perpendicular to the substrate. A vertical distance from a surface of the first area away from the substrate to the substrate is greater than a vertical distance from a surface of the second area away from the substrate to the substrate. The display area includes a second light-shielding layer arranged between the substrate and the planarization layer. In the direction perpendicular to the substrate, a projection of the second light-shielding layer partially overlaps with a projection of the first area.

A display device includes an inorganic insulating layer having a groove surrounding pixel areas, a first thin film transistor in a first pixel area of a substrate, a second thin film transistor in a second pixel area of the substrate, a first electrode layer overlapping a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor, an organic material layer disposed in the groove, a data line extending over the organic material layer in a second direction, and a first connecting line extending across the organic material layer in a first direction, disposed between the first electrode layer and the data line, and overlapping the first electrode layer.

A display apparatus includes an integral integrated circuit and a display panel. The integral integrated circuit includes a gate channel which outputs a gate primitive signal and a data channel which outputs a data voltage. The display panel includes a level shifter which amplifies the gate primitive signal to generate a gate signal. The display panel is configured to display an image based on the gate signal and the data voltage. The display panel includes a first gate line extending in a first direction and a second gate line extending in a second direction. The second direction is different from the first direction. The second gate line is connected to the first gate line. The level shifter is connected to the second gate line.

A display device including a base layer, a circuit layer, a light emitting device layer, an organic layer, and a touch sensing unit. The base layer includes a display area and a non-display area. A plurality of insulation patterns overlaps the non-display area. The organic layer is disposed on the light emitting device and overlaps the plurality of insulation patterns and the organic light emitting diode. At least a portion of the plurality of touch signal lines overlaps the plurality of insulation patterns.

A display device includes a substrate including a first display region, a second display region having an area smaller than that of the first display region, a third display region having an area smaller than that of the first display region, and a non-display region, a plurality of pixels provided in the first to third display regions, a power line which is connected to each of the plurality of pixels and applies a first power voltage to the plurality of pixels, and a fan-out line provided in the non-display region, the fan-out line applying a data signal to the plurality of pixels, where the power line includes an additional power line, a first power line, and disposed on the additional power line, and a second power line disposed on the first power line.

A pixel circuit includes a light emitting element, a first driver transistor, a second driver transistor, and a first compensation capacitor. A first terminal of the first driving transistor is configured to receive a power signal, and a second terminal of the first driving transistor is electrically coupled to the light emitting element. A first terminal of the second driving transistor receives the power signal, and a control terminal of the second driving transistor is electrically coupled to the light emitting element. The first compensation capacitance is electrically coupled to a control terminal of the first driving transistor and the second terminal of the second driving transistor, respectively.

An array substrate has a display area and a peripheral area located outside the display area. The display area includes two first sides that are substantially parallel and arc sides connected to ends of the first sides. The array substrate includes at least one gate driving circuit. Each gate driving circuit includes GOA units sequentially distributed along each arc side in at least one arc side and active GOA units sequentially distributed along a first side connected to the arc side. The GOA units includes at least one active GOA unit and at least one dummy GOA unit. Each active GOA unit is configured to provide a driving signal to at least one sub-pixel. A distance between two adjacent GOA units in the GOA units is approximately same as a distance between two adjacent active GOA units in the active GOA units.

The light emitting display panel includes a plurality of pixels, a plurality of gate lines transferring gate signals to the plurality of pixels, a plurality of data lines transferring data voltages to the plurality of pixels, and a sensing line connected to a plurality of light emitting devices respectively included in the plurality of pixels. Each of the plurality of pixels includes a light emitting device, a sensing control transistor including a first terminal connected to a first terminal of the light emitting device and a gate connected to a sensing control line, and a sensing switching transistor including a first terminal connected to a second terminal of the sensing control transistor, a second terminal connected to the sensing line, and a gate connected to a sensing switching line.

An optical device. The optical device includes an underlying device that is sensitive to input light, and provides output light in a first spectrum based on absorbing the input light. The optical device further includes a stacked device, formed in an active area of a single semiconductor chip, coupled in an overlapping fashion to the underlying device. The stacked device includes first and second zones. Each zone has a plurality of active elements having a particular lateral size, where the lateral size is different for each zone. Each zone also has a plurality of transparent regions formed in the stacked device which are transparent to the light in the first spectrum to allow light in the first spectrum to pass through from the underlying device. The transparent regions are configured in size and shape to cause each zone to have a particular transmission efficiency for light in the first spectrum

Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.