A display device includes: a display unit including a first display area, and a second display area; a scan driver configured to provide a scan signal to each scan line connected to the plurality of first pixels and the plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and the plurality of second pixels, wherein the plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density less than the first density in the second display area, and the plurality of second pixels include at least one sub pixel including one boosting capacitor.

A display device includes: a capacitance wire; a first pixel electrode disposed so as to be adjacent to the capacitance wire; a second pixel electrode disposed so that the capacitance wire is located between the first pixel electrode and the second pixel electrode; a first capacitance forming electrode connected to the first pixel electrode and disposed so as to overlap the capacitance wire via an insulating film; and a shield electrode disposed so as to be located between the first pixel electrode and the second pixel electrode and so as to at least partially overlap the first capacitance forming electrode via an insulating film.

A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.

A display panel includes a pixel circuit that includes a light emitting module, a driving module, a first dual control module, and a second dual control module. A control end of the driving module is connected to a first node. The first dual control module has a control end connected to a first scanning line and has a first end connected to the first node. A first capacitor is formed between an intermediate node of the first dual control module and a first potential line. The second dual control module has a first end connected to the first node and has a second end connected to the driving module. A second capacitor is formed between an intermediate node of the second dual control module and a second potential line. Capacitance of one of the first capacitor and the second capacitor is greater than another.

A display device includes a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and including a first capacitor electrode at least partially overlapping the first semiconductor layer in a plan view to constitute a first transistor, a second capacitor electrode disposed on the first conductive layer and overlapping the first capacitor electrode in a plan view to constitute a first capacitor, a second semiconductor layer disposed on the second capacitor electrode and including a third capacitor electrode overlapping the second capacitor electrode in a plan view to constitute a second capacitor, a second conductive layer disposed on the second semiconductor layer and at least partially overlapping the second semiconductor layer, and a third conductive layer disposed over the second conductive layer to implement a high-resolution image by overlapping the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode.

A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.

A display panel of an OLED display device includes a first pixel configured to emit first color light, a second pixel configured to emit second color light, and a third pixel configured to emit third color light. Each of the first, second and third pixels includes at least two transistors, at least one capacitor and an organic light emitting diode. At least one of at least two transistors or at least one capacitor included in the third pixel has a size different from a size of a corresponding one at least two transistors or at least one capacitor included in the first pixel or the second pixel.

Disclosed are a driving method of an array substrate and an array substrate. The driving method of the array substrate controls a data drive signal line to output a first polarity data drive signal in a first time period and output a second polarity data drive signal in a second time period alternately. In the first time period, the first polarity data drive signal is output to drive the first sub-pixels of each pixel group to make the first sub-pixel of each pixel group to be a first polarity. In the second time period, the second polarity data drive signal is output to drive the second sub-pixel of each pixel group to make the second sub-pixel of each pixel group to be a second polarity. Polarities of sub-pixels of each column are the same.

A pixel driving circuit, a method of driving the same, and a display panel are provided. The pixel driving circuit includes a scanning line, a data line, an organic light emitting diode, a first control switch, a second control switch, and a storage electric capacity. The scanning line drives a control end of the second control switch. An input end of the second control switch is connected to the data line. An output end of the second control switch drives a control end of the first control switch. A first power source signal drives an input end of the first control switch. The organic light emitting diode is coupled between an output end of the first control switch and a second power source signal. The storage electric capacity is coupled between a first reference signal and the control end of the first control switch.

A display device includes a display panel including pixels connected to data lines and scan lines, a data driving circuit which drives the data lines, a scan driving circuit which drives the scan lines, and a driving controller divides the display panel into first and second display regions, controls the data driving circuit and the scan driving circuit to drive the first display region at a first driving frequency and to drive the second display region at a second driving frequency lower than the first driving frequency, and sets third driving frequencies respectively corresponding to horizontal lines in a boundary region, which is defined by a portion of the second display region adjacent to the first display region, during a multi-frequency mode. Each of the third driving frequencies has a frequency level between the first driving frequency and the second driving frequency.