A pixel circuit and a display panel are provided. The display includes the pixel circuit. The pixel circuit includes a data line, a scan line, a plurality of hierarchical 2T1C circuits, a step-down circuit, and a reset circuit. The data line is configured to transmit a source data signal. The scan line is configured to transmit a scan signal. Each input of the plurality of hierarchical 2T1C circuits is connected to the scan line in parallel. An input of the step-down circuit is connected to the data line and an output of the step-down circuit is connected to another input of each 2T1C circuit. The reset circuit is connected to the input of the step-down circuit.

A display device includes subpixels disposed in a display area for displaying an image. Each subpixel includes a light emitting element; a driving transistor for driving the light emitting element; and a transistor whose turn-on or turn-off may be controlled by a gate signal supplied through a gate line. The subpixels includes a subpixel disposed in a specific area in the display area, and such subpixel may include a compensation capacitor formed by overlapping of a gate node of the driving transistor or a connection pattern connected to the gate node of the driving transistor and the gate line. A voltage level of the gate signal supplied through the gate line is changed to a lower voltage level at a timing at which a data voltage or a voltage resulting from changing of the data voltage is applied to the gate node of the driving transistor.

A display panel and a display device are provided, the display panel includes a gate driving circuit, a first pixel module, and a second pixel module, the first pixel module includes a first pixel circuit, and the second pixel module includes a second pixel circuit; the gate driving circuit respectively provides corresponding gate driving signals for the first pixel circuit and the second pixel circuit; in the first display region, the number of columns of the pixel circuit included by the first pixel module is greater than the maximum number of columns of the pixel circuit included by the second pixel module in the second display region; the display panel further includes a loading structure arranged in a non-display region; the load structure is electrically connected to the gate wiring; the gate wiring is wiring between the gate driving circuit and the second pixel circuit for providing the corresponding gate driving signals to the second pixel circuit.

It is an object of the present invention to provide a display device in which problems such as an increase of power consumption and increase of a load of when light is emitted are reduced by using a method for realizing pseudo impulsive driving by inserting an dark image, and a driving method thereof. A display device which displays a gray scale by dividing one frame period into a plurality of subframe periods, where one frame period is divided into at least a first subframe period and a second subframe period; and when luminance in the first subframe period to display the maximum gray scale is Lmax1 and luminance in the second subframe period to display the maximum gray scale is Lmax2, (½) Lmax2<Lmax1<( 9/10) Lmax2 is satisfied in the one frame period, is provided.

An array substrate and a display panel are disclosed; at least one GOA circuit is provided in a pixel area of a same row, all GOA circuits of the same row are connected to a same scan line, and each GOA circuit of the same row is connected to a driving IC through a corresponding driving signal line. By setting the GOA circuit in a display area, a near bezel-free display panel design can be realized. Meanwhile, the GOA circuit is modularly designed to form an independent layout model, which improves design efficiency.

A display device includes: a display unit including a first display area, and a second display area; a scan driver configured to provide a scan signal to each scan line connected to the plurality of first pixels and the plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and the plurality of second pixels, wherein the plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density less than the first density in the second display area, and the plurality of second pixels include at least one sub pixel including one boosting capacitor.

A gate driver includes at least one stage, which includes: a first output circuit configured to supply a voltage of a first power source or a voltage of a second power source to a first output terminal and including a fourth capacitor connected between a second node and the first output terminal; a second output circuit configured to supply a signal supplied to a fourth input terminal or the voltage of the second power source to a second output terminal; an input circuit configured to control a voltage of the second node and a voltage of a third node; a first signal processor configured to control a voltage of a first node; a second signal processor configured to control the voltage of the second node; and a third signal processor connected between the first node and the third node, and configured to control the voltage of the first node.

An emission control driver includes: a plurality of stages having: a first circuit portion configured to generate a first control signal at a first node and a second control signal at a second node; a second circuit portion configured to control a voltage level of the first control signal; a third circuit portion configured to generate a third control signal based on the first control signal, the second control signal, and the second clock signal; a first output transistor configured to output a first voltage as the emission control signal in response to the first control signal; and a second output transistor configured to output a second voltage as the emission control signal, and wherein the third circuit portion comprises a first capacitor configured to maintain a substantially constant voltage between both electrodes while each of the plurality of stages outputs the emission control signal.

A display device includes a display panel having scan lines, data lines, and sub-pixels disposed therein; a scan driver which drives the scan lines; and a data driver which drives the data lines. Each of the sub-pixels includes: a light emitting element; a driving transistor which drives the light emitting element; a 3-1th transistor electrically connected between a first node of the driving transistor and a high potential voltage; a 1-1th transistor and a 1-2th transistor each electrically connected between a second node of the driving transistor and a 1-1th or 1-2th data line, respectively; a second transistor electrically connected between a third node of the driving transistor and an initialization voltage line; a first capacitor connected between the second node and an anode electrode of the light emitting element; and a second capacitor connected between the high potential voltage and the anode electrode.

The present disclosure provides a pixel driving circuit and a display panel. The pixel driving circuit includes: a data writing sub-circuit configured to transmit a data voltage signal to a first terminal of a driving sub-circuit in response to a first scanning signal; a threshold compensation sub-circuit configured to compensate for a threshold voltage of the driving sub-circuit in response to a second scanning signal; a storage sub-circuit configured to store the data voltage signal; the driving sub-circuit configured to provide a driving current for a light emitting device to be driven according to voltages of a first terminal and a control terminal of the driving sub-circuit; and a voltage maintaining sub-circuit configured to maintain the voltage of the control terminal of the driving sub-circuit when the voltage of the first terminal of the driving sub-circuit jumps.