In a display device, transistors are disposed on a display panel. When the display panel has a short-circuit, the timing controller sends a signal to the level shifter to disconnect the transistors, causing the display panel to no longer receive scanning signals transmitted from GOA circuits, causing the display panel enter an overcurrent protection state, and thus preventing GOA wirings in the display panel from burning out in an event of the short-circuit.

A method of driving a light emitting diode (LED) backlight unit, which includes a plurality of LED elements that are connected to a plurality of gate lines and a plurality of source lines, includes generating a plurality of gate signals applied to the plurality of gate lines. While the plurality of gate signals are generated, a non-overlap interval between activation intervals of two adjacent gate signals is generated. All of the plurality of gate signals are deactivated during the non-overlap interval. A plurality of source signals applied to the plurality of source lines are generated. While the plurality of source signals are generated, a high-impedance (Hi-Z) interval included in the non-overlap interval is generated. At least some of the plurality of source signals have a high-impedance state during the high-impedance interval.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

A display device includes a substrate, first electrodes, lines, pixel electrodes, a display functional layer, a common electrode, second electrodes, and a controller. The first electrodes are opposed to the second electrodes with a space therebetween, and an insulating layer is provided between the common electrode and the first and second electrodes. During the display periods, in response to a control signal from the controller, the pixel electrodes are supplied with a pixel signal through the lines, and the common electrode is supplied with a common signal. During the sensing period, in response to the control signal from the controller, the lines are supplied with a first drive signal to generate a magnetic field. The first electrodes are supplied with a second drive signal to generate electrostatic capacitance between themselves and the second electrodes in response to the control signal from the controller, synchronously or asynchronously with the display periods.

Display panels and display devices are provided. The display panel includes a functional module area and a plurality of first signal wirings arranged along a first direction. The display panel includes a first area and a second area, and along the first direction, the functional module area is disposed between the first area and the second area. The plurality of first signal wirings include a plurality of first cross-lines and a plurality of first sub-signal wirings along a second direction, the plurality of first sub-signal wirings are disposed in a display area, the plurality of first cross-lines are connected to the plurality of first sub-signal wirings, and the second direction intersects the first direction. The first area includes M first cross-lines of the plurality of first cross-lines, the second area includes N first cross-lines of the plurality of first cross-lines, and M is greater than N.

Disclosed are a display panel, a driving method therefor, a display device. The display panel includes pixel circuits, data lines, write control lines, compensation control lines, a first driving circuit connected to compensation control lines, a second driving circuit connected to write control lines. Each column of pixel circuits corresponds to one data line, each row of pixel circuits corresponds to one write control line, one compensation control line. The first driving circuit outputs compensation control signals to pixel circuits by compensation control lines, second driving circuit outputs write control signals to pixel circuits by write control lines. The pulse width of compensation control signals is N times pulse width of write control signals, write control signals on two adjacent write control lines do not overlap, an overlap time of compensation control signals on two adjacent compensation control lines is (N-1)/N of pulse width of compensation control signals.

A pixel driving circuit, a display panel and a driving method therefor, and a display device, related to the display field and aiming to enable the pixel driving circuit to work in different operating modes to adapt to various application scenarios. The pixel driving circuit includes a driving transistor, a gate writing module and a control module. The control module and the gate writing module are connected in series on a function signal transmission path between a function signal terminal and a gate electrode of the driving transistor, and the gate writing module is configured to provide a function signal at the function signal terminal to the gate electrode of the driving transistor. An operating process of the pixel driving circuit includes a stage in which the gate writing module is turned on and the control module is turned off.

A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first-to-sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. A second transistor is connected to a first scan carry line and the first Q node. A third transistor is connected to a first sensing carry line and a second sensing carry line. A fourth transistor is connected to a first control line and the third transistor. A fifth transistor is connected to the fourth transistor, a second control line, and a first node. A first capacitor is connected to the fifth transistor. A sixth transistor is connected to a third control line, the first node, and the first Q node.

A scan driving circuit of a display device includes a first output terminal electrically connected to a first scan line, a second output terminal electrically connected to a second scan line, a first masking circuit electrically connecting the first output terminal and the second output terminal and outputting, as a first scan signal, a second scan signal to the first output terminal, a driving circuit outputting the second scan signal to the second output terminal in response to clock signals and a carry signal, and a second masking circuit masking the second scan signal to a predetermined level in response to the second masking signal, wherein the first masking circuit electrically disconnects the first output terminal from the second output terminal in response to a first masking signal.

Embodiments of the present disclosure provide a display device comprising: a substrate; a thin film transistor layer on a first surface of the substrate and including a first hole; a light emitting element layer on the thin film transistor layer and including a light emitting element; a first light blocking layer between the substrate and the thin film transistor layer and including a second hole overlapping the first hole in a thickness direction of the substrate; and a second light blocking layer between the thin film transistor layer and the light emitting element layer and including a third hole overlapping the first hole and the second hole in the thickness direction of the substrate.