An electroluminescent display device comprises a pixel including a plurality of subpixels; a plurality of power lines for providing a power voltage to the plurality of subpixels; a data line for providing data signals to the plurality of subpixels; a plurality of gate lines for providing gate signals to the plurality of subpixels; and a reference node line for connecting a plurality of reference nodes included in the plurality of subpixels, wherein each of the subpixels comprises a light emitting diode and a subpixel driving circuit for controlling light emission of the light emitting diode, and wherein the subpixel driving circuit provides a driving current without including a high potential voltage to the light emitting diode as a reference voltage that is applied from one of the plurality of power lines to the reference node included in the subpixel driving circuit, and some of the plurality of subpixels include a compensation transistor connected to the reference node receiving the reference voltage.

A display substrate and a display device including the display substrate are disclosed. In one aspect, the display substrate includes a plurality of pixels formed in a substantially circular pixel area and a driving circuit formed in a peripheral area surrounding the pixel area and configured to drive the pixels. A boundary is formed between the pixel area and the peripheral area, and the boundary is substantially concentric with respect to an arc defining the substantially circular pixel area. The driving circuit comprises a conductive pattern having a first side which extends in a peripheral direction crossing the boundary.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged in a conductive layer, extend along a first direction and are arranged at intervals along a second direction, and are used to provide initialization signals to the sub-pixels. The connection lines are arranged in another conductive layer, extend along the second direction and are arranged at intervals along the first direction. Projections of at least one initialization signal line and at least one connection line on the base substrate intersect, and the at least one initialization signal line and the at least one connection line are connected through a via hole, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid-like structure.

A display substrate has sub-pixels. Each column of sub-pixels includes first and second sub-pixels alternately arranged. The display substrate includes a base, a second source-drain metal layer including first and second connection portions, and a first source-drain metal layer including first and second data lines alternately arranged. A pixel driving circuit of each first sub-pixel is connected to a second end of a first connection portion, and a first end there is connected to a corresponding first data line. A pixel driving circuit of each second sub-pixel is connected to a second end of a second connection portion, and a first end thereof is connected to a corresponding second data line. In a same column of sub-pixels, an extension direction of a first line connecting a second end of a first connection portion and a second end of a second connection portion is substantially parallel to a second direction.

A display device is provided and includes signal line; pixel electrode; drive electrode opposed to pixel electrode; scanning lines; and display periods and a detection period in frame, wherein during one of display periods, common voltage is applied to drive electrode, scanning signal is applied to some scanning lines, pixel signal is applied to pixel electrode, wherein, during detection period, AC drive or pulse signal is applied to drive electrode, AC drive or pulse signal having pulses, wherein pulses during the detection period is less than number of some of scanning signal lines.

A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a data writing circuit, a driving circuit, a first compensation circuit, a second compensation circuit and a light emitting element. The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current which runs through the first terminal and the second terminal and is used to drive the light emitting element to emit light; the data writing circuit is connected with the control terminal of the driving circuit, and is configured to write a data signal or a reference voltage signal to the control terminal of the driving circuit in response to a scan signal.

A display device comprising a plurality of pixels arranged in multiple rows and multiple columns. The multiple pixel columns are connected with a plurality of source signal lines respectively. The pixels of odd-numbered rows in the same pixel column are connected with the source signal lines on a first side of the pixel column. The pixels of even-numbered rows in the same pixel column are connected with the source signal lines on a second side of the pixel column opposite the first side. A display control method comprising the steps of determining and storing target pixel potential data which comprises a target pixel potential for each of the plurality of source signal lines; and setting a potential of each source signal line as the target pixel potential corresponding to the source signal line in an interval zone between two adjacent frames.

A three-dimensional-image display device includes a display unit, a variable focus lens unit, and a controller. The display unit sequentially displays a first image displayed by a first image signal and a second image displayed by a second image signal, and that projects a display light of the first image and a display light of the second image. The variable focus lens unit switches the focal lengths for the display lights to respectively form, as virtual images, the first image and the second image on a first display surface and a second display surface. The controller controls, on the basis of a start timing at which writing, of an image signal of a different image, to pixels of the display unit starts, a projecting timing at which the display unit projects the display light of the first image and the display light of the second image.

Disclosed is an array substrate. The array substrate includes a substrate and a pixel unit array. A first side of each row of pixel units is provided with a first scanning line corresponding to the row of pixel units, and the first scanning line is connected to switch elements of first-type pixel units in the row of pixel units; and the second side of each row of pixel units is provided with a second scanning line corresponding to the row of pixel units, and the second scanning line is connected to switch elements of second-type pixel units in the row of pixel units. An active layer structure of the switch element of a second-type pixel unit in an i.sup.th row of pixel units has a common region with an active layer structure of the switch element of a first-type pixel unit in an (i+1).sup.th row of pixel units.