A display system circuitry capable of saving power consumption includes a display panel and a driver circuitry. In particular, the display panel includes a plurality of source electrodes with a plurality of data lines and a plurality of gate electrodes further includes a gate driver which is directly incorporated into a thin film transistor array to form Gate on Array (GOA) electrode, a source electrode transmitting a plurality of data driving signals, a gate electrode transmitting gate driving signals, a VCOM electrode transmitting voltage driving signals, a display electrode transmitting displaying driving signals. The driver circuitry includes a display driver IC which includes a source driver operably configured to drive the source electrode and gate control to control gate driver output, and a touch driver IC configured to generate the touch scan signal from a touch sensor.

A gate driver circuit and a display device including the same have a voltage difference between output lines of the gate driver circuit that is reduced. To this end, a first gate driver is disposed on one side of a display panel, while a second gate driver is disposed on side of the display panel opposite the one side. An odd-numbered output line of the first gate driver is connected to an even-numbered output line of the second gate driver, while an even-numbered output line of the first gate driver is connected to an odd-numbered output line of the second gate driver. Therefore, the voltage difference between the output lines of the gate driver circuit is minimized or reduced.

A gate driving circuit includes a first type of stage circuit for outputting a first gate signal and a second type of stage circuit for outputting a second gate signal, and further including a bias transistor for supplying, when turned-on, a bias voltage to a shield metal positioned to overlap with a semiconductor layer of a specific transistor among a plurality of transistors included in the first type of stage circuit, thereby preventing a leakage current from occurring inside the gate driving circuit.

A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.

Embodiments of the present disclosure relate to a data driving circuit, a controller and a display device. A display driving is performed by outputting the number of internal data enable signals that is smaller than the number of external data enable signals in the display device performing high-speed driving. As a result, it is possible to prevent an increase in the load of the data driving circuit according to the high-speed driving. In addition, a part of the internal data enable signals is output during a blank period to prevent a decrease in the interval between the internal data enable signals and to increase the number of internal data enable signals. This can improve the image quality displayed on the display panel while preventing an increase in the load on the data driving circuit.

A method for driving display panel includes: for one of adjacent two frames of displayed images, when scanning odd-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in first order by a data selector;

when scanning even-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in second order by the data selector; first and second orders each represents an order of inputting data signals to the data lines; first order is opposite to second order; for the other of the adjacent two frames of displayed images, when scanning odd-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in second order by the data selector; when scanning even-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in first order by the data selector.

An image dividing circuit includes an input interface circuit that receives input image data configured by a total number of horizontal pixels HT, an image data dividing circuit that divides the input image data into first to n-th output image data, and an output interface circuit that includes output circuits for first to n-th channels that output the first to n-th output image data. The parameter n is an integer greater than or equal to 3, and the parameter HT is not an integer multiple of the parameter n. An output circuit for an i-th channel outputs i-th output image data in which at least one of the total number of horizontal pixels and the total number of vertical lines in the i-th channel has been variably adjusted. The parameter i is an integer greater than or equal to 1 but smaller than or equal to n.

A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Embodiments relate to a display device including an active display area with pixels arranged in rows and columns, where a focus area of the active display area is operated in a progressive scanning manner and a non-focus area of the active display area is operated in an interlaced scanning manner. The active display area is driven by a gate driver circuit that supplies gate signals the pixels. First stages of the gate driver circuit are coupled to first rows of the pixels that are in the focus area and output first gate signals in the progressive scanning manner. Second stages of the gate driver circuit are coupled to second rows of the pixels that are in the non-focus area and output second gate signals in the interlaced scanning manner.

The present disclosure discloses a driving method and apparatus of a display panel. When each of a plurality of obtained display frames is transmitted, only display data, corresponding to each pixel in one row group, in the display frame of image data is transmitted to a driving chip in the display panel, so that the driving chip in the display panel drives the display panel to display an image according to the received display data. Therefore, when a system on chip transmits each of the plurality of obtained display frames, only the display data, corresponding to each pixel in one row group, in the display frame of image data is transmitted to the driving chip in the display panel.