A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.

A display apparatus is disclosed, which includes a pixel. The pixel includes first through fifth transistors and a light emitting element. The first transistor includes a control electrode electrically connected to a first node, an input electrode that receives a first power voltage and an output electrode electrically connected to the light emitting element. The second transistor includes a control electrode that receives a scan signal, an input electrode that receives a grayscale data voltage and an output electrode electrically connected to a second node. The third transistor includes a control electrode electrically connected to the second node, an input electrode that receives a reference voltage and an output electrode electrically connected to the first node. The fourth transistor includes a control electrode that receives the scan signal, an input electrode that receives a bias data voltage and an output electrode electrically connected to the first node. The fifth transistor includes a control electrode that receives a sensing control signal, an input electrode that receives an initialization voltage and an output electrode electrically connected to the light emitting element.

The present disclosure relates to a display device including first pixels disposed in a first pixel area, and connected to first scan lines; second pixels disposed in a second pixel area, and connected to second scan lines; a timing controller configured to supply a first clock signal and a second clock signal to a first clock line and a second clock line, respectively; a first scan driver configured to receive the first clock signal through the first clock line, and to supply a first scan signal to the first scan lines; and a second scan driver configured to receive the second clock signal through the second clock line, and to supply a second scan signal to the second scan lines, wherein the second pixel area has a smaller width than the first pixel area.

Disclosed are a signal processing device and an image display apparatus including the same. The signal processing device of an embodiment of the present disclosure includes: a quality calculator configured to calculate a source quality of an image signal received from an external settop box or a network; an image quality setter configured to set an image quality of the image signal based on the calculated source quality; and an image quality processor configured to perform image quality processing on the image signal based on the set image quality, wherein in response to the source quality of the received image signal being changed at a first time point, the image quality setter changes an image quality setting sequentially from a first setting to a second setting; and based on the image quality setting, the image quality processor performs image quality processing. Accordingly, flicker may be reduced when an image quality is changed due to a change in the source quality of the received image signal.

A display module includes a display panel in which a plurality of pixels each including a plurality of sub-pixels are disposed on a plurality of row lines; and a driver. The driver is configured to set a PWM data voltage to the plurality of sub-pixels included in the plurality of row lines in a row line sequence, apply a sweep signal, which is a voltage signal sweeping between two different voltages, to sub-pixels among the plurality of sub-pixels that are included in at least some consecutive row lines among the plurality of row lines in the row line sequence, and drive the display panel to cause the sub-pixels included in the at least some consecutive row lines to emit light based on the PWM data voltage in the row line sequence.

The invention of the present application provides a drive circuit, a display device, and a drive method for reducing power consumption.

A drive circuit of the present invention includes a setting circuit configured to precharge, to a first voltage, a video signal line connected to a first transistor configured to sample a voltage of the video signal line, and an adjustment circuit configured to adjust a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage during a time period corresponding to a second voltage set in the video signal line.

A display apparatus is disclosed, which includes a pixel. The pixel includes first through fifth transistors and a light emitting element. The first transistor includes a control electrode electrically connected to a first node, an input electrode that receives a first power voltage and an output electrode electrically connected to the light emitting element. The second transistor includes a control electrode that receives a scan signal, an input electrode that receives a grayscale data voltage and an output electrode electrically connected to a second node. The third transistor includes a control electrode electrically connected to the second node, an input electrode that receives a reference voltage and an output electrode electrically connected to the first node. The fourth transistor includes a control electrode that receives the scan signal, an input electrode that receives a bias data voltage and an output electrode electrically connected to the first node. The fifth transistor includes a control electrode that receives a sensing control signal, an input electrode that receives an initialization voltage and an output electrode electrically connected to the light emitting element.

A display device capable of improving image quality is provided. A display device includes a plurality of pixel blocks in a display region. The pixel blocks each include a first circuit and a plurality of second circuits. The first circuit has a function of adding a plurality of pieces of data supplied from a source driver. The second circuit includes a display element and has a function of performing display in accordance with the added data. One pixel has a configuration including one second circuit and an component of the first circuit that is shared. When the first circuit is shared by a plurality of pixels, the aperture ratio can be increased.

An electronic apparatus is disclosed. The electronic apparatus includes a display including a plurality of scan lines arranged in one direction, a plurality of data lines arranged in a direction perpendicular to the plurality of scan lines, a pixel generated in an intersection area of the scan lines and the data lines, and one or more processors configured to provide the scan signal to the plurality of scan lines in an interlaced scanning method based on the image frame being an image in which a first pixel line having high-luminance greater than or equal to a threshold luminance and a second pixel line having low-luminance less than the threshold luminance are alternately arranged

To improve display quality in a case where pixels are driven by using a ramp wave voltage.

A display device includes a plurality of pixel circuits arranged in at least one direction, a plurality of signal lines that supplies the plurality of pixel circuits with signal voltage corresponding to gradation, a voltage output unit that generates ramp wave voltage having a voltage level that changes with time, a ramp wiring that supplies the ramp wave voltage generated in the voltage output unit, a plurality of voltage holding units that is connected between the ramp wiring and the plurality of signal lines, and holds the ramp wave voltage at a timing corresponding to luminance of the plurality of pixel circuits to generate the signal voltage, a plurality of correction current sources that supplies correction current to a plurality of connection paths of the ramp wiring and the plurality of voltage holding units, and a current adjustment unit that adjusts the correction current on the basis of a voltage difference, on a predetermined connection path, of when setting a predetermined luminance to a pixel circuit connected to the predetermined connection path, in a case where the correction current is passed from the plurality of correction current sources to the plurality of connection paths, and in a case where the correction current is not passed from the plurality of correction current sources to the plurality of connection paths.