The present disclosure provides a chip-on-film, a display substrate, a display device and a driving method. The display substrate includes a plurality of scanning lines and a plurality of cascaded shift register units coupled to the scanning lines. The display substrate further includes an output control signal line electrically coupled to each shift register unit for providing an enable signal for the shift register unit. The output control signal lines include at least two output control signal lines for providing different enable signals, and two adjacent cascaded shift register units are coupled to different output control signal lines.

The present disclosure provides a pixel circuit, a display panel and a display apparatus. A gate of a data writing transistor is electrically connected with a first scan line, a first electrode of the data writing transistor is electrically connected with a data line, and a second electrode of the data writing transistor is electrically connected with a first electrode of a drive transistor; a gate of a threshold compensation transistor is electrically connected with a second scan line, a first electrode of the threshold compensation transistor is electrically connected with a gate of the drive transistor, and a second electrode of the threshold compensation transistor is electrically connected with a second electrode of the drive transistor; and a compensation circuit is electrically connected with the gate of the drive transistor.

An input-display device includes a display screen with display pixels, capacitive sensing electrodes for capacitive sensing in a sensing region of the display screen, and a gate driver circuit associated with the display screen. The gate driver circuit superimposes a critical time window on a full-duration gate control pulse of a gate control signal. The critical time window partially overlaps with the full-duration gate control pulse at least at an end of the full-duration gate control pulse. The gate driver circuit further determines that a transient in a sensing waveform of the capacitive sensing occurs in the critical time window superimposed on the full-duration gate control pulse, and based on the determination, shorten the full-duration gate control pulse to obtain a reduced-duration gate control pulse. The gate driver circuit provides the reduced-duration gate control pulse to a pixel circuit of one of the display pixels.

A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.

A display device includes a timing controller, a scan driver, a data driver, and a display unit. The timing controller generates a clock signal, a start signal, and image data. The scan driver includes a plurality of stages for sequentially outputting the clock signal as a scan signal in response to the start signal. The data driver generates a data signal using the image data. The display unit includes pixels for emitting light with a luminance corresponding to the data signal in response to the scan signal. The timing controller performs masking on the clock signal in a part of a first frame period during which the scan driver sequentially outputs the scan signal.

A fingerprint display device has plural pixel rows. Each pixel row of n pixel rows in the plural pixel rows has plural display pixel units and plural fingerprint pixel units, where n is an integer greater than 1. The n pixel rows are driven at least by corresponding n display scan lines and n select lines for performing display and fingerprint detection. Each fingerprint pixel unit has a reset end and a select end. The reset end of the fingerprint pixel unit of i-th pixel row among the n pixel rows is connected to a corresponding display scan line among the n display scan lines, and the select end of the fingerprint pixel unit of i-th pixel row among the n pixel rows is connected to a corresponding select line among the n select lines, where i is an index value between 1 and n.

An electro-optical device includes a plurality of digital scanning lines, a digital signal line, and a plurality of pixel circuits. Each of the pixel circuits includes a light emitting element and a digital driving circuit. The digital driving circuit performs digital driving to turn the light emitting element ON-state or OFF-state based on a grayscale value. The digital driving circuit keeps the light emitting element ON-state by supplying a drive current to the light emitting element, in a period in which an enable signal is active, of a grayscale display period having a length corresponding to the grayscale value. The control line driving circuit sets a period in which the enable signal is active. A ratio, with respect to the grayscale display period, of an ON-state period in which the light emitting element is ON-state changes in accordance with the period in which the enable signal is active.

Provided are a display panel, a drive method thereof and a display apparatus. The display panel includes M*N display units disposed in an array defined by intersections of (M+1) gate lines and N pairs of data lines, and each pair of data lines include a first data line and a second data line; in an m.sup.th display row, display units of odd display columns are connected to an m.sup.th gate line, and display units of even display columns are connected to an (m+1).sup.th gate line; in an n.sup.th display column, display units of odd display rows are connected to first data lines of an n.sup.th pair of data lines, and display units of even display rows are connected to second data lines of the n.sup.th pair of data lines.

Provided is a display panel which may include a pixel array including a plurality of pixels connected to scan lines and data lines, a photonic synapse block including a plurality of photonic synapse elements, and a neuron block including a plurality of neuron elements electrically connected to the plurality of photonic synapse elements.

A pixel circuit includes: a light emitting element having one end connected to a first power line supplying a first power voltage; a driving transistor for controlling an amount of current flowing to a second power voltage via the light emitting element electrically connected to a first electrode the driving transistor; an initialization transistor connected between a second electrode of the driving transistor and an initialization power line supplying an initialization voltage, the initialization transistor having a gate electrode connected to a first scan line; a compensation transistor connected between the first power line and the first electrode of the driving transistor, the compensation transistor having a gate electrode connected to a second scan line; and a storage capacitor connected between a gate electrode of the driving transistor and the second electrode of the driving transistor.