The present disclosure relates to a display device and a driving method thereof, wherein a refresh rate of pixels is controlled at a reference frame frequency in a normal driving mode, and the refresh rate of the pixels is controlled at a frequency lower than the reference frame frequency in a low speed driving mode. In the low speed driving mode, park data is transmitted to a data driving circuit during at least one vertical blank period.

The present disclosure provides a pixel driving circuit, a method of driving the same, and a display device. In the pixel driving circuit, under the control of a gate line, a data writing-in sub-circuit controls to connect or disconnect a data line and a first common node, and controls to connect or disconnect the first common node and a gate electrode of the driving transistor; under the control of a reset signal line, a first reset control sub-circuit controls to connect or disconnect a reference voltage input terminal and a second common node, and controls to connect or disconnect the second common node and the gate electrode of the driving transistor; a first end of a third capacitor unit is connected to the first common node and/or the second common node, and a second end of the third capacitor unit is connected to the first electrode of the driving transistor.

The flicker performance manager disclosed herein implements a method including measuring a liquid crystal (LC) common voltage (VCOM) over a predetermined period of operation an LCD panel having a plurality of LCs, determining a shift in the VCOM (VCOM shift) over the predetermined period based at least in part on the measured VCO, storing the VCOM shift as a function of time in a table of an embedded controller, receiving a power-on signal for the LCD panel and adjusting a VCOM reference level applied to the LCs based at least in part on the stored values of the VCOM shift.

A display panel and a display device are provided. The display panel includes a plurality of light emitting points; a plurality of pixel driving circuits, wherein at least one of the plurality of light emitting points is connected to at least one of the plurality of pixel driving circuits; and a plurality of electrode leads, the at least one of the plurality of light emitting points is connected to the at least one of the plurality of pixel driving circuits through at least one of the plurality of electrode leads; the plurality of pixel driving circuits are separated from the plurality of light emitting points.

Methods for efficiently clearing previous state information when driving a multi-particle color electrophoretic medium, for example, wherein at least two of the particles are colored and subtractive and at least one of the particles is scattering. Typically, such a system includes a white particle and cyan, yellow, and magenta subtractive primary colored particles. The clearing pulse may include two different portions of alternating impulses and the overall waveform may be DC balanced.

A signal line capacitance compensation circuit and a display panel are provided, a signal line capacitance compensation circuit includes: a plurality of signal lines; at least one control line, a compensation capacitor being provided between the control line and at least one of the plurality of signal lines; and a signal source configured to send a charging signal to one or more control lines of the at least one control line, the charging signal being used to charge the compensation capacitor between the one or more control lines receiving the charging signal and the at least one signal line.

A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.

An electroluminescent display device having a plurality of pixels is disclosed. Each pixel includes a driving transistor having a gate connected to a first node, a source connected to a third node, and a drain connected to a fourth node, to generate pixel current corresponding to a data voltage when a high-level source voltage is applied to the third node, a light emitting element connected between the fourth node and an input terminal for a low-level source voltage, an internal compensator including first and second capacitors, and switching transistors, and a kick-back compensation transistor to apply a DC voltage higher than an initialization voltage to the first node in a kick-back compensation period between an initialization period and a data writing period.

The present disclosure discloses a display panel drive method and drive device. A display panel includes source driver units distributed on two opposite sides of the display panel and the source driver units are longitudinally or transversely alternately connected to data lines of the display panel. During display drive, a processor controls an input signal of a system end to be output as a data signal and a control signal, then controls, according to the data signal, the source driver units to charge the respectively connected data lines of the display panel, and finally controls a gate drive signal to be input according to the control signal to display the input signal.

An electrophoretic display having a plurality of display pixels, each of the plurality of display pixels may include a pixel electrode for driving the display pixel, a single thin film transistor (TFT) coupled to the pixel electrode for transmitting waveforms to the pixel electrode, a front plane laminate (FPL) coupled to the single thin film transistor, and a storage capacitor coupled to the pixel electrode and placed in parallel with the FPL, where the storage capacitor is configured to be sufficiently ohmically conductive to allow the discharge of remnant voltages from the FPL through the storage capacitor.