A display panel includes a first pixel group and a second pixel group each including sub-pixels coupled to the first scan line, a third pixel group and a fourth pixel group each including sub-pixels coupled to the second scan line. The first pixel group and the second pixel group are driven during a first scan on time in which the first scan line is driven. Consecutive N−1 sub-pixels among the sub-pixels of the third pixel group and one sub-pixel among the sub-pixels of the fourth pixel group are driven during a first portion of a second scan on time in which the second scan line is driven, and consecutive N−1 sub-pixels among the sub-pixels of the fourth pixel group and one sub-pixel among the sub-pixels of the third pixel group are driven during a second portion of the second scan on time.

A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

An information processing apparatus (30) includes: an estimation unit (33B) that estimates the crosstalk amount based on a relative positional relationship between a viewing position of a viewer of a display device (10) and a pixel a screen of the display device (10); and a generation unit (33C) that generates an image to be displayed on the display device (10) by correcting a value of each of a plurality of pixels of the screen based on the crosstalk amount.

The present application discloses a display device capable of performing favorable display in which flicker is not visually recognized while the power consumption of a scanning-side drive circuit, as well as a data-side drive circuit, can be reduced sufficiently when pause driving is performed. A pixel circuit including emission control transistors M5, M6 in addition to a drive transistor M1 includes a switching element that is turned on based on a voltage of an emission control line Ei to initialize an organic EL element OL when the voltage of the emission control line Ei is at a level for turning off the emission control transistors M5, M6. For example, in some embodiments, the anode electrode of the organic EL element OL is connected to an initialization voltage line Vini via an N-channel transistor M7 serving as the switching element, and the emission control line Ei is connected to the gate terminal of the transistor M7. In the pixel circuit, the transistors M1, M5, M6, and the like except for the transistor M7 are all P-channel transistors.

Device comprising: a rear panel comprising a network of backlighting elements, a front panel comprising a network of optical valves which are each capable of modulating the brightness of a single primary colour. By the modulation of chrominance which is added to the modulation of luminance for the backlighting elements of the rear panel, the device according to the invention makes it possible to display the images with even more contrast and better quality. A specific control mode makes it possible to avoid the colour “interferences”.

A novel functional panel that is highly convenient, useful, or reliable is provided. The functional panel includes a first element, a first reflective film, and an insulating film. The first element includes a first electrode, a second electrode, and a layer containing a light-emitting material; the layer containing a light-emitting material includes a region interposed between the first electrode and the second electrode; the first electrode has a light-transmitting property; and the first electrode has a first thickness. The first electrode is interposed between a region of the first reflective film and the layer containing a light-emitting material, and the first reflective film has a second thickness. The insulating film includes a first opening portion, and the first opening portion overlaps with the first electrode. The insulating film has a first step-like cross-sectional shape, and the first step-like cross-sectional shape surrounds the first opening portion. The first step-like cross-sectional shape includes a first step, and the first step is larger than or equal to a thickness obtained by adding the second thickness to the first thickness.

An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. The respective one of the plurality of voltage supply lines is connected to the interference preventing block through a third via. The interference preventing block includes a first arm and a second arm. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm.

The present disclosure provides a display substrate, a method for driving the same, and a display device. The display substrate includes: a plurality of sub-pixels, a plurality of reset signal lines, a plurality of gate lines, a plurality of light emitting control signal lines, a plurality of data lines, a power signal line structure, an initialization signal line structure, and at least part of the reset signal lines extend along the first direction; the plurality of reset signal lines include a sub-reset signal line corresponding to each sub-pixel, and the sub-reset signal line includes a first reset pattern and a second reset pattern that are coupled to each other, the first reset pattern is located between the substrate of the display substrate and the second reset pattern.

A display panel and a display device are provided. The display panel includes a substrate; a driving circuit layer, disposed on the substrate and including a reset signal line and a first power signal line; a light-emitting element layer, including organic light-emitting elements, wherein each organic light-emitting element includes a first electrode, a light-emitting layer, and a second electrode, and the light-emitting layer includes a first common layer, a light-emitting material layer and a second common layer; and a compensation capacitor, disposed between at least two adjacent organic light-emitting elements and including a first plate and a second plate insulated from each other, wherein the first plate is disposed on a side of the first common layer facing the substrate and in contact with the first common layer and electrically connected with the reset signal line, and the second plate is electrically connected with the first power signal line.

A display panel and a display device are provided. The display panel includes: a display part including a plurality of data lines; a fan-out part including a plurality of fan-out lines; and a lead wire part including a plurality of first lead wires which are respectively connected with the plurality of data lines through the plurality of fan-out lines, and the plurality of fan-out lines are fanned out between the lead wire part and the display part. The plurality of first lead wires each include a first lead wire subpart and a compensation part to form a plurality of first lead wire subparts and a plurality of compensation parts, the plurality of first lead wire subparts are respectively connected with the plurality of compensation parts; the first lead subparts (WS1) have a width different from that of the compensation parts.