Disclosed are a display panel having a large area, high resolution, a narrow bezel, low power consumption, and having reduced Resistance Capacitance (RC) delay, and a display device including the same. The display panel includes an Active Area Gate-In-Panel (AAGIP) disposed between adjacent pixel blocks, wherein the AAGIP unit is configured to: connect an n scan line disposed in and along sub-pixels of an n-th row of the pixel block on one side of the AAGIP unit and an n scan line disposed in and along sub-pixels of an (n+1)-th row of the pixel block on the other side thereof to each other; and connect an n+1 scan line disposed in and along sub-pixels of an (n+1)-th row of the pixel block on one side thereof and an n+1 scan line disposed in and along sub-pixels of an n-th row of the pixel block on the other side thereof to each other. Thus, defect such as crosstalk or smear caused by data line transition is reduced.

A light emitting diode (LED) matrix driver includes a scan line switch coupled to a scan line of an LED matrix and adapted to be coupled to a signal ground; a first voltage clamp coupled to the scan line switch and the scan line; and a second voltage clamp coupled to the scan line.

A display device includes a display panel including a plurality of pixels which display an image, a panel driver which generates a driving voltage based on a plurality of feedback voltages sensed from the display panel to drive the display panel, and a plurality of sensing lines which are connected to the pixels to sense the feedback voltages, respectively, and apply the sensed feedback voltages to the panel driver. The panel driver generates an average feedback voltage corresponding to an average of the feedback voltages and generates the driving voltage based on the average feedback voltage.

A display device include a substrate on which a plurality of first sub-pixels disposed in first columns and a plurality of second sub-pixels disposed in second columns are defined; a plurality of data lines disposed on one sides of the plurality of first sub-pixels and the other sides of the plurality of second sub-pixels; and a plurality of parking voltage lines disposed between the plurality of first sub-pixels and the plurality of second sub-pixels, wherein the plurality of parking voltage lines are configured to be electrically connected to some of the plurality of data lines. Accordingly, by applying the same parking voltage to the parking voltage lines and the data lines during a blank frame, flicker can be reduced.

A driving chip includes a data channel block including a plurality of data channels, a scan channel block disposed in a first direction from the data channel block and including a plurality of scan channels, a data pad block disposed outside the data channel block and the scan channel block in the first direction and including a plurality of data pads which respectively receive a data signal from the plurality of data channels, and a scan pad block disposed outside the data channel block and the scan channel block in the first direction, disposed outside the data pad block in a second direction crossing the first direction and including a plurality of scan pads which respectively receive a scan signal from the scan channels.

A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After a threshold voltage of the transistor is held by the capacitor, a potential in accordance with a video signal is inputted and a voltage that is the sum of the threshold voltage and the potential is held. Accordingly, variation in current value caused by variation in threshold voltage of the transistor can be suppressed. Therefore, a desired current can be supplied to a load such as a light emitting element. In addition, a display device with a high duty ratio can be provided by changing a potential of the power supply line.

A display device includes: a display unit including a first display area, and a second display area; a scan driver configured to provide a scan signal to each scan line connected to the plurality of first pixels and the plurality of second pixels; and an emission controller configured to provide an emission control signal to each emission control line connected to the plurality of first pixels and the plurality of second pixels, wherein the plurality of first pixels have a first density in the first display area, the plurality of second pixels have a second density less than the first density in the second display area, and the plurality of second pixels include at least one sub pixel including one boosting capacitor.

A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

An organic light emitting display device includes a plurality of pixels. Each of the pixels includes an organic light emitting diode, first to third transistors, a storage capacitor, and a first capacitor. The second transistor includes a gate electrode receiving a first scan signal, a first electrode receiving a data signal, and a second electrode connected to a first electrode of the first transistor. The third transistor includes a gate electrode receiving a second scan signal, a first electrode connected to a second electrode of the first transistor, and a second electrode connected to a gate electrode of the first transistor. The storage capacitor includes a first electrode receiving a power voltage and a second electrode connected to the gate electrode of the first transistor. The first capacitor includes a first electrode connected to the gate electrode of the third transistor and a second electrode receiving the power voltage.

Embodiments of the disclosure relate to a display device and a data driving circuit. Specifically, there may be provided a display device with enhanced power efficiency and a data driving circuit by providing a display device including a display panel divided into an always-on display area displaying information during a standby screen period and a black grayscale area except for the always-on display area, an image display voltage output circuit outputting a data voltage to input to the always-on display area during the standby screen period, and a voltage stabilization circuit outputting a constant voltage to input to at least a partial area of the black grayscale area during the standby screen period.