An EL display includes a flexible board including: a plurality of connection terminals arranged at one side for connection with panel lines formed on a panel board; terminal connection lines for connecting points inside the flexible board with the connection terminals; serial connection lines for connecting between two or more of the connection terminals. On the flexible board: driver output terminals of each of gate driver ICs are connected to terminal connection lines; driver input terminals of the gate driver IC are connected to either terminal connection lines or the serial connection lines; and control terminals for performing logic setting of the gate driver IC are each arranged between connection terminals and driver input terminals to which the serial connection lines are connected. As a result, the number of control lines to be formed on the flexible board in serial connection is reduced.

An active matrix organic light-emitting diode (AMOLED) display device and a controlling method thereof. The AMOLED display device (100) comprises a system power IC (110), a driver IC (120), an AMOLED panel (130), a power line (111) and a feedback line (112). The AMOLED panel (130) includes a plurality of pixel circuits. The system power IC (110) outputs a positive power supply voltage (ELVdd1) to the plurality of pixel circuits via the power line (111), and the driver IC (120) detects a positive power supply voltage (ELVdd2) actually applied to the plurality of pixel circuits via the feedback line (112) and compensates for data voltages (Vdata) based on the positive power supply voltage (ELVdd2) actually applied to plurality of pixel circuits. The driving chip detects the positive power supply voltage (ELVdd2) actually applied to plurality of pixel circuits, and automatically adjusts a minimum grayscale voltage (VREG1) and a maximum grayscale voltage (VGS) based on the positive power supply voltage (ELVdd2) actually applied to the plurality of pixel circuits, such that a certain difference value can be maintained between the data voltage (Vdata) and the positive power supply voltage (ELVdd2) actually applied to the plurality of pixel circuits, thus eliminating Gamma offset.

A display device includes a substrate having a first pixel region, a second pixel region having a smaller area than the first pixel region, the second pixel region being connected to the first pixel region, and a peripheral region surrounding the first pixel region and the second pixel region, a first pixel and a second pixel respectively at the first and second pixel regions, a first line connected to the first pixel and a second line connected to the second pixel, and a dummy unit in the peripheral region, the dummy unit overlapping with at least one of the first and second lines, the dummy unit being configured to compensate for a difference between a load value of the first line and a load value of the second line, wherein the dummy unit includes at least two sub-dummy units spaced from each other.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

The present invention reliably and sufficiently corrects a voltage variation in data signal lines in a display device resulting when sampling analog video signals, while suppressing increase in layout area. In a data signal line drive circuit of an active matrix liquid crystal display device, a video signal Svi is sampled by an Nch transistor (SWk) which has a parasitic capacitance (Cgd) that causes a voltage drop in a data signal line SL3(i−1)+k (i=1 through n; k=1, 2, 3). To correct this, an inversion delayer (342) makes logical inversion of the transistor (SWk)'s control signal Sck and delays the inverted signal for a predetermined time to generate an inversion delayed signal Srdk, and applies this inversion delayed signal Srd to the data signal line 3(i−1)+k via a correction capacitance element (Cc). The inversion delayer (342) makes the inversion delayed signal Srdk start its change from an L level voltage to a H level voltage after the Nch transistor (SWk) has assumed an OFF state.

A display device includes a display area including a plurality of pixels and a plurality of scan lines connected to the plurality of pixels, and a driving circuit portion that generates a compensation data voltage to compensate for a difference in length between the plurality of scan lines to input the compensation data voltage to a pixel disposed in a first area, based on start scan line information indicating a start of the first area including scan lines of the plurality of scan lines, and end scan line information indicating an end of the first area.

A thin-film transistor (TFT) array substrate is provided. The TFT array substrate is structured to change the way that sub-pixels are arranged so that during a displaying period of a frame of image, the sub-pixels that have inconsistent brightness/darkness become alternate with each other spatially so that a displaying defect of vertical bright/dark lines can be improved and the overall resistance of the data line can be reduced to thereby reduce resistance-capacitance delay and prevent incorrect charging at a tail end of a scan line or a data line.

A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.

A display panel and a display device are provided. The display panel includes: a display region and a peripheral region surrounding the display region. The display region comprises a first display sub-region and a second display sub-region. The width-to-length ratio of a channel region of an output transistor in a second gate shift register corresponding to the second display sub-region is decreased so as to reduce the charging time of pixels in the second display sub-region, so that the brightness of the pixels in the second display sub-region is consistent with the brightness region of pixels in the first display sub-region. The configuration facilitates achieving a narrow bezel while improving the display uniformness of the display panel without changing the existing circuit structure and occupying the additional bezel area.

A sensing circuit and a correction method thereof, a pixel driving module and a sensing method thereof, and a display apparatus, the sensing circuit includes: an operation amplifier (AMP), an integration capacitor (Cfb), a first switch (S1), a second switch (S2), a third switch (S3), a fourth switch (S4), a fifth switch (S5) and a sixth switch (S6).