The present disclosure provides a source driver, a display device, and a driving method. A plurality output channels of at least one source driver are grouped into a plurality of groups, and the plurality of output channel groups are provided with at least one multi-level voltage compensation unit. The at least one multi-level voltage compensation unit is configured to output compensation voltages, and then data voltages are outputted. As such, pixels in the display device can have the same charging voltage in the same time.

A pixel includes a light-emitting device, a driving TFT for controlling a magnitude of a current from a power line to the light-emitting device according to a gate-source voltage, a storage capacitor disposed between the power line and a gate of the driving TFT, a scan TFT to transfer a data voltage to a source of the driving TFT in response to a first signal, first and second compensation TFTs serially connected between a drain and the gate of the driving TFT, a gate initialization TFT to apply a first voltage to the gate of the driving TFT in response to a second signal, an anode initialization TFT to apply a second voltage to an anode of the light-emitting device in response to a third signal, and a shield capacitor disposed between a node between the first and second compensation TFTs and the power line or a second voltage line.

This display device according to an aspect of the disclosure includes a pixel circuit including: a drive transistor configured to control an electric current for a light-emitting element; a switching circuit; and a first capacitive element and a second capacitive element both connected to the switching circuit, wherein the switching circuit connects the first capacitive element to a control terminal of the drive transistor in a first period that falls within a single frame period and connects the second capacitive element to the control terminal of the drive transistor in a second period that falls within the single frame period and that follows the first period.

A data drive circuit, a drive method for data drive circuit and an organic light emitting display that has the data drive circuit. The data drive circuit has a data signal multiplexing structure, and also comprises a power source line (50) for connecting to a power source (Vref) and second transistors (T2′ . . . Tm′) connected to the power source line (50), the second transistors (T2′ . . . Tm′) have source electrodes electrically connected to the power source line (50), gate electrodes electrically connected to the same line (Sel_1) of the control lines, and drain electrodes respectively electrically connected to different lines (Dj′) of the signal lines at a connection point between a first transistor (T1 . . . Tm) and the display area (40). By connecting a compensation power source (Vref) to the signal lines (D1′ . . . Dm′) for initializing the pixel units (11 . . . mm), the influence of stray capacitance in the pixel units (11 . . . mm) is alleviated, thereby effectively improving the response properties and display properties of an organic light emitting display apparatus equipped with this data drive circuit.

A display apparatus includes a display panel including data lines, first to n.sup.th data driver integrated circuits (ICs) (n being a natural number greater than 1) supplying data voltages to the data lines, a controller controlling the first to n.sup.th data driver ICs, and a power supply supplying power to the first to n.sup.th data driver ICs, the first data driver IC includes a lock signal switching unit receiving or blocking a lock signal from the power supply, a pull-up resistor is provided between the second data driver IC and a lock signal line to which the lock signal is supplied from the power supply, and the lock signal supplied to the first data driver IC or the second data driver IC is transferred to the controller through the first to n.sup.th data driver ICs.

A gate driving circuit that can be stably driven by improving output characteristics of a last output buffer unit, and a display device comprising the gate driving circuit, are discussed. The gate driving circuit can include a plurality of subordinately connected stages, where an Nth (N being a natural number) stage includes a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal. The Nth stage can further include a plurality of scan pulse output units configured to receive a plurality of scan clocks, and output each of the scan clocks as a scan pulse according to voltages of the first node and the second node.

A timing control circuit is provided to control a data voltage outputted to a pixel array of a display panel during a frame period to perform a polarity reversal every N scan lines, where N is a positive integer. The timing control circuit includes a receiver and an adjustment circuit. The receiver is configured to sequentially receive first display data and second display data for one data line of the display panel. The adjustment circuit is coupled to the receiver to adjust at least one of gray information of the second display data and charging time of the second display data according to a voltage polarity of the first display data and a voltage polarity of the second display data. A corresponding operation method of the timing control circuit is also provided.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

A display assembly includes a display unit having a liquid crystal layer and an LED array configured to illuminate the liquid crystal layer. A driver circuit is operatively connected to the LED array and configured to control a luminance of the LED array. A control module is operatively connected to the display unit and includes a processor and tangible, non-transitory memory on which is recorded instructions for executing a method for controlling the LED array in the display unit. The control module is programmed to obtain a junction temperature (T.sub.J) of the LED array, via the driver circuit. The junction temperature (T.sub.J) is based at least partially on a first voltage (V.sub.1), a second voltage (V.sub.2) and a predetermined coefficient (T.sub.coefficient). The control module may be programmed to enter one of a plurality of stages based at least partially on the junction temperature (T.sub.J).

Systems, methods, and apparatuses are disclosed for overcoming latency and loss of signal detection in remote control displays. An exemplary system includes a remote control, a host computing device, and one or more target systems communicatively coupled to each other over a wired and/or wireless network. One method includes receiving, by the remote control and from a host computing device, a first video frame captured by a target device, determining a first time corresponding to receipt of the first video frame, receiving, from the host computing device, a second video frame, determining a second time corresponding to receipt of the second video frame, comparing the time difference to a latency threshold, and causing an alert graphic element to be displayed indicating a latency in communication.