A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

A pixel includes a driving transistor connected to an organic light emitting diode. The circuit places the driving transistor in an on-biased state based on first and second scan signals which at least partially overlap during a time when an organic light emitting diode does not emit light. The first and scan signals are received from different scan lines. The scan lines may be adjacent scan lines.

A display device operating at high speed is provided. The display device includes a pixel provided with a first memory circuit, a second memory circuit, and a display unit, in which the first memory circuit and the second memory circuit are electrically connected to one electrode of the display unit. The operation of the display device includes a first period of writing first image data to the first memory circuit and writing second image data to the second memory circuit, a second period of supplying a first potential to the first memory circuit, a third period of displaying a first image corresponding to the first image data, a fourth period of setting a potential of the one electrode of the display unit to a second potential, a fifth period of supplying the first potential to the second memory circuit, and a sixth period of displaying a second image corresponding to the second image data.

A display driver comprises: a first grayscale line; output circuitry configured to receive a first grayscale voltage from the first grayscale line and perform digital-analog conversion on a pixel data to output a source output voltage corresponding to the pixel data, the digital-analog conversion being based on the first grayscale voltage; and first gamma assist circuitry comprising a first holding node to hold the first grayscale voltage received from the first grayscale line and configured to drive the first grayscale line based on a first voltage between the first holding node and the first grayscale line.

A display device includes: a plurality of pixel blocks each including a plurality of pixels; a scan driver supplying a scan signal to the scan lines and to supply a control signal to the control lines; a data driver supplying an image data voltage or a low grayscale data voltage to the data lines; and a power supply supplying a reference voltage to the pixels, wherein the pixels are configured to receive the image data voltage during a first scan period of a frame, and to receive the low grayscale data voltage during a second scan period of the frame, and the reference voltage supplied to a first pixel row of at least one of the pixel blocks in the first scan period is different from the reference voltage supplied to a last pixel row of at least one of the pixel blocks in the first scan period.

A pixel structure is provided to increase a response speed of liquid crystal and includes a first thin-film transistor, a second thin-film transistor, an upper substrate, a lower substrate opposite to the upper substrate, pixel electrodes arranged on the lower substrate, a common electrode arranged on the upper substrate, and assisting electrodes arranged on the lower substrate. The assisting electrodes are arranged to be each sandwiched between every two pixel electrodes. The first thin-film transistor includes a first drain terminal, a first source terminal, and a first gate terminal. The second thin-film transistor includes a second drain terminal, a second source terminal, and a second gate terminal. The pixel electrodes are electrically connected to the second drain terminal. The assisting electrodes are electrically connected to the first drain terminal.

A circuit. In some embodiments, the circuit includes: a drive circuit having an output and including: a pre-emphasis circuit; and an output stage connected to an output of the pre-emphasis circuit. The pre-emphasis circuit may be configured to generate, during a first interval of time, a pre-emphasized signal. The output stage may be configured to produce, at the output of the drive circuit, a constant signal based on the pre-emphasized signal during the first interval of time, and to disconnect the pre-emphasis circuit from the output of the drive circuit during a second interval of time, the second interval of time beginning at the end of the first interval of time.

A pixel driving circuit and driving method thereof, an array substrate and a display device. The pixel driving circuit can maintain a voltage difference between two terminals of a storage capacitor (Cst) when a gate line scanning is ended. The pixel driving circuit comprises a pixel thin film transistor (T0) and a storage capacitor (Cst), wherein a gate of the pixel thin film transistor (T0) is connected to a gate line, a first terminal of the pixel thin film transistor (T0) is connected to a data signal (Data), a second terminal of the pixel thin film transistor (T0) is connected to a first terminal of the storage capacitor and a second terminal of the storage capacitor (Cst) is grounded. The pixel driving circuit further comprises a follow module connected the first terminal of the storage capacitor (Cst), and configured to maintain a voltage difference between two terminals of the storage capacitor (Cst) when a gate scanning signal (Gate(n)) makes a transition from a high level to a low level, so as to enable the pixel electrode to obtain sufficient voltage thereby ensuring the display effect of the liquid crystal display.

The present invention provides a display device driving method and a display device. The method directly loads compression de-mura data in a compressed state into a memory during booting, which enhances a booting speed. Decoding only performed for current display position when images are displayed, which lowers occupation of the memory. Furthermore, multi-thread parallel decoding of the de-mura data is achieved by identifiers and decoding modules, which drastically increases a decoding speed.

A monitor includes a timing controller coupled to a liquid crystal display panel. A scaler unit receives a change event notification associated with a change to a new overdrive setting of the liquid crystal display panel, and determines a set of lookup table values associated with the change to the new overdrive setting of the liquid crystal display panel. The scaler unit determines a size of data to be transmitted based on the set of lookup table values, and divides the data to be transmitted into data portions based on factors that include the size of the data to be transmitted, speed of an inter-integrated circuit bus, or length of a vertical blank period. The scaler unit then transmits one of the data portions during the vertical blank period via the inter-integrated circuit bus.