A method comprises monitoring a drawing time of a first frame of image, obtaining a current state of a system on chip (SOC) when the drawing time exceeds a first drawing duration, where the current state comprises a current temperature of the SOC and/or a current load of the SOC, determining whether the current state exceeds a first preset threshold, when the current state does not exceed the first preset threshold, increasing an operating frequency of the SOC in a time range, and restoring the operating frequency after the increasing of the operating frequency ends, obtaining actual drawing duration of the first frame of the image when drawing of the first frame of the image is completed, and monitoring a drawing time of a second frame of the image when the actual drawing duration does not exceed second drawing duration.

A display device includes a display panel including a plurality of pixels; a gate driver for applying a gate-on signal through a plurality of gate lines of the display panel; a data driver for applying a data signal through a plurality of data lines of the display panel; and a timing controller for controlling the gate driver and the data driver to display an image frame at a first frame frequency. The display panel is driven at a second frame frequency that is higher than the first frame frequency. The timing controller controls the gate-on signal to be applied to the plurality of gate lines for a time determined on the basis of the second frame frequency, and controls the data driver to apply an over driven data signal to the plurality of data lines.

The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

A display driver includes a D/A converter circuit outputting a gradation voltage to an output line based on display data, an assist circuit including a capacitor group and a drive circuit outputting a drive signal group to a first end of the capacitor group based on the display data, the assist circuit being coupled to the output line and configured to perform assist driving of the output line, and an amplifier circuit configured to drive an electro-optical panel. The assist circuit includes an output switch provided between a second end of the capacitor group and the output line, the output switch being ON in an assist period, and an initialization switch including a first end coupled to the second end of the capacitor group and a second end to which an initialization voltage is input, and in an initialization period, the output switch and the initialization switch are ON.

It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

An image display method for a head mounted display (300) is disclosed. The head mounted display (300) includes a first display screen (3011) and a second display screen (3012). In a first time period S1 of an i.sup.th display cycle T, the head mounted display (300) displays an i.sup.th frame of a first image on the first display screen (3011). After stopping displaying the i.sup.th frame of the first image, the head mounted display (300) displays an i.sup.th frame of a second image on the second display screen (3012) in a second time period S2 of T. After the second time period, no image is displayed on the first display screen (3011) and the second display screen (3012). According to the method, a peak current of a device when displaying an image can be reduced.

The present disclosure provides a display method, a computer storage medium, and a display device. The display method includes: detecting a frame image including a still image; accumulating a retention time of the still image in the frame image, the retention time is a time for uninterruptedly displaying the still image; determining whether the accumulated retention time is greater than a threshold value; sequentially shifting data of the frame image by n rows in response to that the accumulated retention time is greater than the threshold value, the threshold value is an accumulated value of the retention time when a line afterimage begins to appear on the still image; a row direction of the n rows is a scanning direction of the frame image; wherein 1≤n≤3N/4, N is a total number of rows scanned for one frame image, n is an integer, and 3N/4 is rounded to an integer.

An electronic device is provided. The electronic devices includes a display, a memory, and a processor configured to be operatively connected to the display and the memory. The processor is configured to generate a main thread related to a user input and data processing on an application in response to execution of the application and a render thread related to rendering image data in units of frames based on data processed in the main thread, configure a target frame rate for displaying an execution screen of the application on the display, calculate an expected processing time of a current frame based on a processing time of at least one previous frame output through the display, determine a time margin based on the target frame rate and the calculated expected processing time, and perform the user input and data processing after the main thread waits in a sleep state for the time margin.

A display controller for a display may include a frame rate circuit to change a frame rate of the display from a first frame rate to a second frame rate, and a reference voltage circuit to adjust a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate. The display may be a thin film transistor liquid crystal display. The reference voltage may correspond to a common voltage (Vcom) for the display.