To provide a pixel circuit capable of suppressing a decrease in luminance due to leakage of a transistor without increasing the number of elements or with a minimum increase in the number of elements even if the number is increased. A pixel circuit is provided including a light-emitting element, a drive transistor configured to supply a current to the light-emitting element, a first reset transistor configured to set a potential of an anode of the light-emitting element to a predetermined potential, a first write transistor configured to control writing of a signal voltage at a gate node of the drive transistor, a holding capacitance having one end connected to the gate node of the drive transistor and configured to hold a threshold voltage of the drive transistor, and a second write transistor connected in series between the gate node of the drive transistor and the first write transistor.

The present application discloses a drive circuit, a. display module driving method and a display module. The drive circuit includes: a timing control chip, configured to output a state signal; a control circuit, configured to receive the state signal and output a ready signal; and a gate drive circuit, configured to control, according to the ready signal, whether a display screen displays a picture or not.

Systems and methods are provided for generating an overdrive look-up table (LUT) for response time compensation of a display device are described. In some embodiments, an Information Handling System (IHS) may include a controller and a memory coupled to the controller, the memory having program instructions stored thereon that, upon execution, cause the controller to generate a Look-up Table (LUT) of alternate grey levels selected to implement Response Time Compensation (RTC) in a Liquid Crystal Display (LCD), where at least one of the alternate grey levels is calculated, at least in part, by taking into account a frame rate of a video stream.

Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

[Object] To provide a display apparatus that can achieve enhancement in display performance of a screen and higher definition.

[Solution] There is provided a display apparatus. The drive circuit includes a drive transistor configured to control the light emitting unit, a video signal writing transistor configured to control writing of a video signal, and a capacitative element. In the drive transistor, one source/drain region is connected to a current supply line, another source/drain region is connected to the light emitting unit and a first node of the capacitative element, and a gate electrode is connected to a second node of the capacitative element. In the video signal writing transistor, one source/drain region is connected to a data line, another source/drain region is connected to the gate electrode of the drive transistor and the second node of the capacitative element, and a gate electrode is connected to a scanning line. The drive transistor and the video signal writing transistor are different in carrier mobility.

The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.

The transistor comprises a first insulation layer and at least one switch region; a first function layer and a second function layer are respectively disposed on each side of the first insulation layer in the x direction; a first source is disposed in a source region of the first semiconductor layer, and a first drain is disposed at a drain region of the first semiconductor layer; a second source is disposed in a source region of the second semiconductor layer, and is connected to the first source by a first connection line; a second drain is disposed in a source region of the second semiconductor layer, and is connected to the first drain by a second connection line; the gate structure is insulated from the first semiconductor layer and the second semiconductor layer and is disposed opposite to channel regions of the first semiconductor layer and the second semiconductor layer.

Embodiments of the present invention disclose an information processing method. The method comprises: receiving an acquisition request sent by a terminal for acquiring an image to be displayed, wherein the acquisition request carries an identifier of the image, and the image comprises a first object to be displayed and a second object to be displayed; acquiring, on the basis of the acquisition request, the image corresponding to the identifier, and performing identification on the image to obtain a first image region and a second image region, wherein the first image region comprises the first object, and the second image region comprises the second object; and determining a sending order, and sequentially sending, according to the sending order, the first image region and the second image region to the terminal. Also disclosed by the embodiments of the present invention are a server, a terminal, and a computer storage medium.

A processing system reduces latency and improves predictability of a scan out position to support graphics processing unit (GPU) front buffer rendering with a variable refresh rate (VRR) display. The GPU detects whether front buffer rendering such as inking is occurring on a frame-by-frame basis. In order to maintain a safe distance from the current scan out position and achieve low latency to improve the user experience, the GPU increases the refresh rate of the VRR display to a low-latency (high-frequency) fixed refresh rate in response to detecting front buffer rendering. In some embodiments, the GPU decreases the refresh rate in response to detecting a static screen to save power.

A display device capable of improving image quality is provided. The display device includes a first circuit, a pixel, and a wiring. The first circuit has a function of supplying data to the wiring and a function of making the wiring floating to hold the data. The pixel has a function of taking in the data twice from the wiring and performing addition. The pixel can perform the first writing of the data in a period during which the data is supplied to the wiring, and can perform the second writing of the data in a period during which the data is held in the wiring. Therefore, by one lime of data charging to a source line, a data potential larger than or equal to an output voltage of a source driver can be supplied to a display element.