Disclosed are a driving method of an array substrate, an array substrate and a display panel. The array substrate includes a plurality of sub-pixels, a plurality of row scan drive signal lines, a plurality of data drive signal lines and a plurality of common electrode signal lines. The plurality of sub-pixels are arranged in an array, each row of sub-pixels are divided into a first pixel group and a second pixel group. The sub-pixels of the first pixel group and the second pixel group are arranged alternately in the row. Each of the data drive signal line is provided between two columns of sub-pixels of each group, and electrically connected to each sub-pixel of two columns of sub-pixels of each group. Each of the data drive signal lines is provided between the two columns of sub-pixels of each group.

A dual-system device and writing method and apparatus thereof, and interactive intelligent tablet includes a first system and a second system receiving touch data, where the data rendering speed of the first system is faster than that of the second system, and the data processing speed of the second system is faster than that of the first system; the first system acquiring data to be rendered from a target storage area, where the data to be rendered is generated by the second system according to the touch data and stored in the target storage area; the first system rendering the data to be rendered to obtain handwriting data to be displayed, and transmitting the handwriting data to be displayed to a display screen of the dual-system device for display. The disclosure solves the technical problem of writing delay of an external system when using dual-system to perform writing.

An output buffer is provided, which including an input circuit, output circuits, a first multiplexer, a second multiplexer and a demultiplexer. The input circuit is for generating a first control signal and a second control signal according to a feedback signal and an input signal. Each output circuit is controlled by a first gate signal and a second gate signal to provide a corresponding one of output signals. The first multiplexer is for providing the first control signal and the second control signal to one of the output circuits as the first gate signal and the second gate signal, respectively. The second multiplexer is for providing a first reference voltage and a second reference voltage as the first gate signal and the second gate signal, respectively, to other of the output circuits. The demultiplexer is for providing one of the output signals as the feedback signal.

This disclosure describes efficient communication of surface texture data between system on a chip (SOC) integrated circuits. An example system includes a first integrated circuit and a second integrated circuit communicatively coupled to the first integrated circuit by a video communication interface. The first integrated generates a superframe in a video frame of the video communication interface for transmission to the second integrated circuit. The superframe includes multiple subframe payloads that carry surface texture data to be updated in the frame and corresponding subframe headers that include parameters of the subframe payloads. The second integrated circuit includes a direct access memory (DMA) controller. The DMA upon receipt of the superframe, writes the surface texture data within each of the subframe payloads directly to an allocated location in memory based on the parameters included in the corresponding one of the subframe headers.

A controller to drive a display includes a voltage code generator and a voltage code compensator. The voltage code generator is configured to generate a first voltage code to drive pixels in the display based on input image data. The voltage code compensator is to generate a second voltage code to drive the pixels by compensating zero-grayscale codes of the first voltage code based on the zero-grayscale codes of the first voltage code, one-grayscale codes of the first voltage code, and the input image data.

In an embodiment, an electronic device includes an electronic display. The electronic display provides a programmable latency period in response to receiving a first image frame corresponding to first image frame data. The electronic display also displays the first image frame after the programmable latency period and during display of the first image frame, receives a second image frame corresponding to second image frame data. The electronic display also repeats display of the first image frame in response to receiving the second image frame.

A display device is disclosed. The display device comprises: a display panel; a memory storing information on a compensation value according to a change in gray scale of an input image, which is preconfigured according to a driving frequency of the display panel; a timing controller for controlling the display panel to display a current frame of the input image, on the basis of information stored in the memory; and a processor for acquiring a target gray scale value of the current frame on the basis of a frequency of the current frame, acquiring a compensation value corresponding to the acquired target gray scale value, and controlling the timing controller to display the current frame on the basis of the acquired compensation value.

Systems and methods are provided for generating an overdrive look-up table (LUT) for response time compensation of a display device are described. In some embodiments, an Information Handling System (IHS) may include a controller and a memory coupled to the controller, the memory having program instructions stored thereon that, upon execution, cause the controller to generate a Look-up Table (LUT) of alternate grey levels selected to implement Response Time Compensation (RTC) in a Liquid Crystal Display (LCD), where at least one of the alternate grey levels is calculated, at least in part, by taking into account a frame rate of a video stream.

This document describes systems and techniques for delaying anode voltage reset for quicker response times in organic light-emitting diode (OLED) displays. In an aspect, a pixel circuit includes a transistor electrically connected to an anode of an organic light-emitting diode and a reset voltage. Upon receiving an anode reset signal, the transistor completes the circuit causing the anode voltage to reset to the reset voltage in an anode voltage reset process. Delaying anode voltage reset can hasten response times in OLED displays.

An electroluminescent display device using a variable refresh rate (VRR) mode. The occurrence of a difference in luminance at a time point of a refresh rate change is reduced, thereby preventing viewers from perceiving the change of the refresh rate.