In an odd frame, a plurality of scanning lines are selected sequentially, and in one pixel circuit, when a scanning line corresponding to the one pixel circuit is selected, a first selector electrically couples one end of a first capacitance element to a data line, and a second selector electrically couples one end of a second capacitance element to the gate node of a transistor. In an even frame, the plurality of scanning lines are selected sequentially, and when the scanning line is selected, the first selector electrically couples one end of the second capacitance element to the data line, and the second selector electrically couples one end of the first capacitance element to the gate node.

A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.

A multiplexed, synchronized active beam splitter or mirror and display providing a user or manufacturer with the ability to choose different modes of functionality of a transparent optical module.

Provided is display device comprising a substrate; a first semiconductor layer disposed on the substrate and having a plurality of transistors; a second semiconductor layer disposed on the first semiconductor layer and having a plurality of transistors; a first data conductive layer disposed on the second semiconductor layer; a first metal layer disposed on the first data conductive layer; and a second metal layer disposed on the first metal layer, wherein the first metal layer includes a first storage electrode and a first input electrode, the second metal layer includes a second storage electrode and a second input electrode, the first storage electrode and the second storage electrode configure a storage capacitor, and the first input electrode and the second input electrode configure an input capacitor.

A measurement system for measuring a motion picture response time (MPRT) of a liquid crystal display (LCD) has a computer and a measurement device. The computer controls a display panel of the LCD to switch between a plurality of different gray levels. The measurement device measures variations of brightness of the display panel when the display panel switches its gray level. The computer obtains at least a gray level response time (GLRT) normalized curve according to results of measuring the variations of the brightness. The computer integrates the at least a GLRT normalized curve to obtain at least an MPRT normalized curve, obtains at least a time interval of the at least an MPRT normalized curve, and calculates an average of the at least a time interval to obtain the MPRT of the LCD.

When, in a liquid crystal projector, optical responsiveness of a liquid crystal panel corresponding to G is better than optical responsiveness of a liquid crystal panel corresponding to R, a display control circuit performs a tr correction and a tf correction of overdrive processing for R, and performs only the tr correction of the overdrive process for G, and does not perform the tf correction for G. The display control circuit performs a black floating process for R, G, and B.

Embodiments of the subject matter described herein relate to a wireless programmable media processing system. In the media processing system, a processing unit in a computing device generates a frame to be displayed based on a graphics content for an application running on the computing device. The frame to be displayed is then divided into a plurality of block groups which are compressed. The plurality of compressed block groups are sent to a graphics display device over a wireless link. In this manner, both the generation and the compression of the frame to be displayed may be completed at the same processing unit in the computing device, which avoids data copying and simplifies processing operations. Thereby, the data processing speed and efficiency is improved significantly.

A display device may include a data driver that outputs a previous data voltage and a current data voltage, respectively, at an output terminal, to be applied to a pixel of a display panel in respective time intervals. A switch is controlled to open and close a circuit path between the output terminal and a data line coupled to the pixel. A capacitor stores an overdriving voltage. At least one further switch selectively applies the overdriving voltage to the data line from the capacitor when the circuit path is open and thereby enables a rapid transition of a voltage level of the data line between the previous and current data voltages, when the current and previous data voltages are to differ by more than a predetermined amount. As an example, the rapid transition between the previous and current data voltages may serve to minimize a color mixture phenomenon between pixels connected to a common data line and representing different colors.

Disclosed are a row drive circuit of array substrate and a display device. The row drive circuit includes N row drive units (10) arranged in cascade and auxiliary circuit units. The N.sup.th row drive unit (10) is configured to output N.sup.th gate driving signal to pre-charge and charge the N.sup.th row of sub-pixels, when its signal input end receives the gate driving signal output by (N−2).sup.th row drive unit (10). The N.sup.th auxiliary circuit unit (20) is configured to control N.sup.th row drive unit (10) skip pre-charging the sub-pixels, when (N−1).sup.th timing control signal received by the first timing signal input end of N.sup.th auxiliary circuit unit and (N+1).sup.th timing control signal received by the second timing signal input end of N.sup.th auxiliary circuit unit are high level. N is positive integer greater than or equal to two.

A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.