G09G2330/021

Driving circuit and display panel

A driving circuit and a display panel are disclosed. The driving circuit includes a plurality of cascaded driving units. The driving unit includes a forward/backward scan control module, a first control node controlling module, a second control node controlling module, a global control module, a regulating module, a first output module configured to output a stage signal, and a second output module configured to output a gate driving signal. A voltage level of the gate driving signal is higher than a voltage level of the stage signal.

COMPARATOR CIRCUIT AND DRIVER
20230015972 · 2023-01-19 ·

A comparator circuit according to this embodiment includes: a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit configured to hold a data of a data input terminal based on a comparator clock signal and configured to output an enable signal for stopping an operation of the comparator element; and an internal signal generation circuit configured to output an internal signal to the data input terminal based on the matching signal and an output signal output from the flip-flop circuit.

COMPARATOR CIRCUIT AND DRIVER
20230020460 · 2023-01-19 ·

A comparator circuit according to the present embodiment: including a comparator element configured to output a matching signal indicating whether or not a value of a first input signal matches a value of a second input signal; a flip-flop circuit including a data input terminal to which a constant potential is supplied and a clock input terminal and configured to hold a value of the data input terminal based on a self-clock signal input to the clock input terminal; and a clock generation circuit configured to generate the self-clock signal based on the matching signal.

ELECTRONIC DEVICE AND METHOD OF OPERATING THE SAME
20230016151 · 2023-01-19 ·

An electronic device according to an example embodiment may include a fingerprint sensor configured to perform at least one of a fingerprint detection function of detecting a fingerprint and an illuminance measurement function of measuring an illuminance value in a light receiving area. The electronic device may include a display configured to display an image on a panel based on a changed luminance The electronic device may include a processor configured to: activate a light receiving area of at least a portion of the fingerprint sensor based on whether the display is activated, and change a luminance of the display based on an illuminance value measured from the light receiving area in an off state in which pixels arranged on a panel of the display do not display an image.

PANEL DRIVING ARCHITECTURE, DRIVING METHOD, AND DISPLAY DEVICE
20230017629 · 2023-01-19 ·

A panel driving architecture is provided in the disclosure. The panel driving architecture includes a circuit board module and a panel module electrically coupled with the circuit board module. The circuit board module includes a power management circuit and a signal management circuit. The power management circuit is electrically coupled with the panel module and the signal management circuit. The power management circuit is configured to provide an operating voltage for the panel module and the signal management circuit. The signal management circuit is electrically coupled with the panel module and configured to: provide a first scanning signal, convert the first scanning signal into a second scanning signal, output the second scanning signal to the panel module, provide a first data signal, convert the first data signal into a second data signal containing a data signal, and output the second data signal to the panel module.

POWER MANAGEMENT INTEGRATED CIRCUIT AND ITS DRIVING METHOD
20230018128 · 2023-01-19 · ·

The present disclosure relates to a power management integrated circuit and a gate clock modulation circuit, the power management integrated circuit including a delay circuit configured to delay, by a preset time, and output an on clock signal for setting an output start time point of a gate driving circuit and an off clock signal for setting an initialization time point of the gate driving circuit; a multiplexer configured to select and output one among delayed signals transferred through signal lines which are connected to the delay circuit; and a gate clock generation circuit configured to generate a gate clock signal by using the on clock signal and the off clock signal outputted from the multiplexer.

Power management integrated circuit and its driving method
11705050 · 2023-07-18 · ·

A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

Pixel and display device including the same

A pixel of display device includes a light emitting element, a first transistor coupled between first power source and a second node and having a gate electrode connected to a first node N1, and the first transistor being configured to control a driving current supplied to the light emitting element in response to a voltage of the first node, a first capacitor including one electrode connected to the first node and another electrode connected to a third node, a second transistor coupled between the third node and a data line, a third transistor coupled between the first node and the second node, a fourth transistor coupled between the first node and an initialization power source, a fifth transistor coupled between a reference power source and the third node, and an eighth transistor coupled between a fourth node and an anode initialization power source.

DISPLAY APPARATUS

Provided is a display apparatus including a modular display panel that includes a plurality of displays disposed in a matrix form and respectively including a display panel including a pixel array in which pixels including a plurality of inorganic light emitting elements are disposed in a plurality of row lines, sub-pixel circuits respectively corresponding to inorganic light emitting elements of the pixel array, a driver configured to drive the sub-pixel circuits, a sensor configured to sense a current flowing in a driving transistor included in the sub-pixel circuits and output sensing data corresponding to the sensed current, and a processor configured to correct the image data voltage applied to the sub-pixel circuits based on the sensing data, and a timing controller configured to provide a first start signal to a driver of a first display and a second start signal to a driver of a second display.

DISPLAY APPARATUS

A display apparatus, including a display panel which includes a pixel array including a plurality of pixels arranged in a plurality of row lines, and a plurality of sub-pixel circuits, wherein each pixel of the plurality of pixels includes a plurality of inorganic light emitting elements, and wherein each sub-pixel circuit of the plurality of sub-pixel circuits corresponds to an inorganic light emitting element of the plurality of light emitting elements; and a driver configured to drive the plurality of sub-pixel circuits so that the plurality of inorganic light emitting elements emit light a plurality of times in an order of the plurality of row lines based on an image data voltage corresponding to one image frame, wherein the each sub-pixel circuit includes a discharge transistor configured to remove a potential difference between both ends of a corresponding inorganic light emitting element based on a predetermined cycle