A pixel driving circuit and a display panel are provided, and adopt a pixel driving circuit of 5T1C structure to effectively compensate the threshold voltage of the driving transistor in each pf the pixels. The pixel driving circuit can effectively reduce leakage power consumption of a pixel driving circuit when extracting a threshold voltage, thereby improving compensation accuracy of the pixel driving circuit.

A method of driving a display panel includes dividing an input image into a plurality of segments, generating a flicker value of a segment of the plurality of segments, determining whether to compensate the flicker value of the segment or not according to a segment size, compensating the flicker value of the segment based on the segment size, determining a frame rate of the display panel based on the flicker value of the segment and outputting a data voltage to the display panel in the frame rate. The flicker value of the segment is compensated based on the flicker value of the segment and flicker values of segments that are adjacent to the segment.

A scan driver includes stages, each of the stages receiving first and second clock signals having a first low level as an active level, and a third clock signal having a high level as the active level. Each of the stages includes a logic circuit that changes a voltage of a first node to the first low level based on an input signal and the first clock signal, and changes a voltage of the first node to a second low level lower than the first low level based on the second clock signal, a first output buffer that outputs, as an active-low scan signal, the second clock signal in response to the voltage of the first node, and a second output buffer that outputs, as an active-high scan signal, the third clock signal in response to the voltage of the first node.

An electronic equipment and a display driving system are provided. The display driving system includes a power management circuit and a timing circuit electrically connected to the power management circuit. The power management circuit receives an input voltage and output a working voltage according to the input voltage. The timing circuit receives the working voltage and output a predetermined command to the power management circuit. The power management circuit is further configured to select a predetermined working mode according to the predetermined command such that the power management circuit works in the predetermined working mode.

A power voltage generator includes a charge pump and a regulator. The charge pump generates a charge pumping voltage. The charge pumping voltage has a headroom margin which is automatically set. The charge pumping voltage is varied based on a target voltage. The regulator generates a power voltage based on the charge pumping voltage.

Provided are a pixel circuit, a method for driving the pixel circuit, and a display panel. The pixel circuit includes a drive transistor including a gate terminal, a source terminal, a drain terminal, and a body terminal, where the source terminal is connected to a first power line, the body terminal is connected to a second power line, and the gate terminal of the drive transistor is connected to a gate potential control circuit; the first power line is configured to provide a first voltage or a second voltage, where the first voltage is higher than the second voltage; and the second power line is configured to provide the fixed first voltage.

A display device may include a display unit, a signal controller, and a sensing unit. The display unit may include pixels. The signal controller may select a first pixel set from the pixel according to ages of the pixels determined based on an image signal. The sensing unit may be electrically connected to each of the display unit and the signal controller and may sense deterioration information of one or more pixels included in the first pixel set for a vertical blank period in which the display unit displays no image.

A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one. A respective column of the N columns of light emitting controlling units includes M number of groups of second voltage signal lines, a respective group of the M number of groups of second voltage signal lines connected to a respective one of the M number of light emitting controlling units, the respective group of the M number of groups of second voltage signal lines including k number of second voltage signal lines, k is an integer equal to or greater than one.

A display device according to an embodiment includes a plurality of pixel blocks including a plurality of pixels connected to a plurality of scan lines and a plurality of data lines, respectively, and at least one active circuit; and a data driver supplying a data voltage to the plurality of data lines in a light emitting mode and supplying a neural network input signal to the plurality of data lines in an artificial neural network mode. In the artificial neural network mode, a scan signal is supplied to a scan line connected to at least one pixel block among the plurality of pixel blocks, and the neural network input signal is supplied to a data line connected to the at least one pixel block.

A gate driving circuit and a display device including the same are disclosed. The gate driving circuit includes a plurality of signal transmitters which are cascade-connected via a carry line to which a carry signal is applied from a previous signal transmitter, and a repair line connected to the plurality of signal transmitters, wherein a signal transmitter includes a circuit part to receive the carry signal from the previous signal transmitter, and charge or discharge a first control node and a second control node, an output part to output a gate signal and a carry signal based on potentials of the first control node and the second control node, and a repair block connected to the repair line and to output a repair gate signal replacing the gate signal and a repair carry signal replacing the carry signal when a logic signal is applied from the repair line.