The present embodiments disclose a pixel driving circuit. A pixel driving circuit according to an embodiment of the present disclosure is electrically connected to a luminous element and comprises a first circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes included in a frame, a second circuit configured to store bit values of multi-bit data in the frame and generate the control signal based on the stored bit values, and a clock signal such that each subframe included in the frame is controlled according to each bit value, and wherein each of the plurality of subframes includes a data-writing period and a light-emitting period, during the data-writing period of each subframe, the second circuit receives and stores a corresponding bit string from among a plurality of bit strings of n-bit data, wherein the plurality of bit strings are generated by a combination of bits in the number of n, which is smaller than m, from among m bits constituting a bit string of the multi-bit data, and the n-bit data is a bit string in which n bits from among the m bits are combined such that a difference in light-emitting periods of the plurality of subframes is minimized.

A current limiting circuit is a circuit that receives a video signal for a display panel including pixels, and limits current consumption of the pixels. The current limiting circuit includes: a first gain calculation circuit that calculates a first gain for multiplying with the video signal, based on first power consumption that is power consumption of the pixels corresponding to the video signal; a second gain calculation circuit that calculates a second gain for multiplying with the video signal, based on the first power consumption and a rate of change of the first power consumption; a gain selection circuit that selects one of the first gain and the second gain as a gain by which the video signal is to be multiplied; and a gain multiplication circuit that multiplies the video signal by the gain.

A display device includes light emitting elements arranged in a matrix and pixel circuits arranged in a matrix. A pixel circuit includes a first reset sub-circuit, a node control sub-circuit, a light emitting control sub-circuit and a second reset sub-circuit. The first reset sub-circuit is configured to provide a signal of an initial signal line to a first node. The node control sub-circuit is configured to provide a signal of a data signal line to a second node, and compensate the first node until a voltage of the first node meets a threshold condition. The light emitting control sub-circuit is configured to provide a signal of a first power supply line to the second node and provide a signal of a third node to a light emitting element. The second reset sub-circuit is configured to provide a signal of the initial signal line to the light emitting element.

A pixel circuit comprises a first switch element comprising a first electrode to which an initialization voltage is applied, a gate electrode to which a initialization pulse is applied, and a second electrode connected to a second node; a second switch element comprising a first electrode connected to a third node or a fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied; a third switch element comprising a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; and a fourth switch element comprising a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node.

A display device includes a display panel including a plurality of pixels, a controller configured to output image data and a gated clock signal, the image data including a plurality of pixel data for the plurality of pixels, and a data driver configured to receive the image data and the gated clock signal from the controller, and to sample the image data in response to the gated clock signal. The controller detects a repeated data pattern where same pixel data is repeated in the image data, generates a clock enable signal having an off level in a period in which the repeated data pattern is transferred, and gates an input clock signal in response to the clock enable signal to produce the gated clock signal.

A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

A second display region has a lower pixel density than a first display region. A third metal layer is located upper than a first metal layer and a second metal layer. The occupancy of the third metal layer in the second display region is lower than the occupancy in the first display region. In a pixel unit, the first metal layer includes a first electrode region to control an amount of electric current in a driving transistor, the second metal layer includes a second electrode region and a third electrode region to supply current to the driving transistor, and the third metal layer includes a main region to form a capacitor included in a capacitive element to store a control voltage for the driving transistor, and an island region surrounded by the main region with a gap and interconnected with a lower electrode region by a via region.

A display device includes: a data distribution circuit between a display area and a data driving circuit in a peripheral area, wherein the data distribution circuit includes: a plurality of first demultiplexers configured to receive a data signal output via a first output line from the data driving circuit and to transmit the data signal to a pair of first data lines from among the plurality of data lines; and a plurality of second demultiplexers configured to receive, through a corresponding conductive line from among the plurality of conductive lines, a data signal output via a second output line from the data driving circuit and to transmit the data signal to a pair of second data lines from among the plurality of data lines.

Home screen contents may be provided simultaneously while a communication terminal switches to an active mode from an inactive mode. The home screen contents correspond to an application installed in the communication terminal, and a user may set an application which desires the home screen contents to selectively receive the home screen contents.

A display device includes a pixel unit including first pixels disposed in a first area and second pixels disposed in a second area, an emission driver configured to sequentially supply emission signals of a turn-off level to the first pixels and the second pixels based on a first start signal, a first clock signal, and a second clock signal, and a first scan driver configured to sequentially supply first scan signals of a turn-on level to the first pixels based on a second start signal, the first clock signal, and the second clock signal, and sequentially supply the first scan signals of the turn-on level to the second pixels based on a third start signal, the first clock signal, and the second clock signal.