Patent classifications
G09G2360/121
Regional adjustment of render rate
- Eric J. Asperheim ,
- Subramaniam Maiyuran ,
- Kiran C. Veernapu ,
- Sanjeev S. Jahagirdar ,
- Balaji Vembu ,
- Devan Burke ,
- Philip R. Laws ,
- Kamal Sinha ,
- Abhishek R. Appu ,
- Elmoustapha Ould-Ahmed-Vall ,
- Peter L. Doyle ,
- Joydeep Ray ,
- Travis T. Schluessler ,
- John H. Feit ,
- Nikos Kaburlasos ,
- Jacek Kwiatkowski ,
- Altug Koker
In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
RENDERING PIPELINE FOR TILED IMAGES
Features are disclosed for rendering an image using a GPU and CPU based rendering pipeline. An imaging system may include a GPU and a CPU that each include a portion of an image renderer. A component of the GPU can process the set of image tiles to generate a texture with a wrapped tile coordinate. A component of the GPU can further store the image data as a level of a texture pyramid. As subsequent image data is received, a component of the GPU can access the texture pyramid to determine previously stored image tiles. A component of the GPU can use the previously stored image tiles in rendering the subsequent image data.
Ray tracing system architectures and methods
Aspects comprise systems implementing 3-D graphics processing functionality in a multiprocessing system. Control flow structures are used in scheduling instances of computation in the multiporcessing system, where different points in the control flow structure serve as points where deferral of some instances of computation can be performed in favor of scheduling other instances of computation. In some examples, the control flow structure identifies particular tasks, such as intersection testing of a particular portion of an acceleration structure, and a particular element of shading code. In some examples, the aspects are used in 3-D graphics processing systems that can perform ray tracing based rendering.
Apparatus and method for power management of a computing system
A multiple graphics processing unit (GPU) based parallel graphics system comprising multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having an object division mode of operation. Each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem. According to the principles of the present invention, pixel (color and z depth) data buffered in the video memory of each GPU is communicated to the video memory of a primary GPU, and the video memory and the pixel processing subsystem in the primary GPU are used to carry out the image recomposition process, without the need for dedicated or specialized apparatus.
LIGHT FIELD DEVICE, OPTICAL ABERRATION COMPENSATION OR SIMULATION RENDERING METHOD AND VISION TESTING SYSTEM USING SAME
Described are various embodiments of a light field device, optical aberration compensation or simulation rendering method and vision testing system using same. In one embodiment, the device comprises a digital display comprising a set of pixels; an array of light field shaping elements (LFSE) disposed relative to the set of pixels so to at least partially govern a light field emanated thereby; and a digital processor operable to: receive as input one or more higher order aberration parameters digitally defining a higher order aberration; for each given pixel, identify an adjusted image plane location corresponding thereto given a corresponding LFSE corresponding thereto and given said one or more higher order aberration parameters, and associate therewith an adjusted image value designated for the adjusted image location; and render for each said given pixel said adjusted image value associated therewith.
Display control system, display apparatus and control method
Provided are a display module control system, a display apparatus, a control method, a computer device and a medium. The display module control system includes a display module, a display controller driving the display module and a bridge unit connecting the display module and the display controller, wherein the display controller is configured to output a first video signal according to an external video source; the bridging unit is configured to determine whether the display controller is in normal operation state according to the first video signal received, output the first video signal to the display module to play the first video signal when the display controller is in normal operation state, and output a second video signal pre-stored to the display module to play the second video signal when the display controller is not in normal operation state.
Systems and method for virtual reality video conversion and streaming
A video server is configured to convert frame data of a spherical image to frame data of a equirectangular image such that a first area corresponding to a field of view received from a client device is a middle area of the equirectangular image. The video server is further configured to scale the first area at a first resolution, scale a second area of the equirectangular image adjacent to the first area at a second resolution smaller than the first resolution, scale a third area of the equirectangular image that is adjacent to the first area and is not adjacent to the second area, at a third resolution smaller than the first resolution, and rearrange the scaled first area, second area and third area such that the scaled second area and the scaled third area are adjacent to each other, to generate reformatted equirectangular image frame data to be encoded.
Apparatus and method for efficient graphics virtualization
An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.
SYSTEMS AND METHOD FOR GPU BASED VIRTUAL REALITY VIDEO STREAMING SERVER
Systems and methods of processing and streaming a virtual reality video using a graphics processing unit (GPU) are provided. A video server is configured to cause a processor to read, from a video data source, source video data including multiple spherical image frame data and store the source video data in a first memory. The video server is further configured to cause the GPU to convert, in response to storing first spherical image frame data in a first frame buffer of a second memory, the first spherical image frame data to first equirectangular image frame data that correspond to a portion of spherical image represented by the first spherical image frame data, encode the converted first equirectangular image frame data and store the encoded first equirectangular image frame data in an encoded frame buffer of the second memory.
COMPUTE OPTIMIZATION MECHANISM
An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.