Described are various embodiments of a light field device, optical aberration compensation or simulation rendering method and vision testing system using same. In one embodiment, the device comprises a digital display comprising a set of pixels; an array of light field shaping elements (LFSE) disposed relative to the set of pixels so to at least partially govern a light field emanated thereby; and a digital processor operable to: receive as input one or more higher order aberration parameters digitally defining a higher order aberration; for each given pixel, identify an adjusted image plane location corresponding thereto given a corresponding LFSE corresponding thereto and given said one or more higher order aberration parameters, and associate therewith an adjusted image value designated for the adjusted image location; and render for each said given pixel said adjusted image value associated therewith.

Described are various embodiments of a light field vision-based testing device, system and method. One such device comprises an array of digital display pixels; a corresponding array of light field shaping elements (LFSEs); a hardware processor operable to adjust perception of a defined optotype within a range of visual acuity compensations; and an adjustable refractive optical system adjustable to selectively produce a complementary visual acuity compensation to extend each of a cylindrical compensation range and a spherical compensation range.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

Provided are a display module control system, a display apparatus, a control method, a computer device and a medium. The display module control system includes a display module, a display controller driving the display module and a bridge unit connecting the display module and the display controller, wherein the display controller is configured to output a first video signal according to an external video source; the bridging unit is configured to determine whether the display controller is in normal operation state according to the first video signal received, output the first video signal to the display module to play the first video signal when the display controller is in normal operation state, and output a second video signal pre-stored to the display module to play the second video signal when the display controller is not in normal operation state.

A method and apparatus for processing graphic data, which are capable of decreasing a bandwidth of a memory, are provided. The method of processing graphic data includes receiving first graphic data and processing the first graphic data to generate second graphic data, and storing the generated second graphic data in a first shared memory line in which a state bit is set to a first state, wherein the first shared memory line is included in a first memory line set which is a part of an n-way set associative cache structure (n is a natural number equal to or greater than 2), at least one of the memory lines of the first memory line set is set to a second state which is different from the first state, and the state bit represents whether data stored in the memory line is replaceable.

An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if the draw call's fragment passes for all pixels, it indicates that tile will contain exactly the same pixel color values as the previous frame. Hence, there is no requirement to run the pixel shader for the tile of pixels, and the color values of the tile can instead be reused from the previous frame.

A semiconductor device with low power consumption is provided. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of processing image data using a parameter. The image processing portion takes the image data from a frame memory and takes the parameter from the register. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller has a function of controlling power supply to the register, the frame memory, and the image processing portion.

Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.

A method, computer program product, and system for adjusting a dynamic refresh frequency of a display device are disclosed. The method includes the steps of obtaining a current frame duration associated with a first image, computing, based on the current frame duration, a repetition value for a second image, and repeating presentation of the second image on a display device based on the repetition value. The logic for implementing the method may be included in a graphics processing unit or within the display device itself.

In response to detection of a selection of an accelerated frame rate operation associated with a video advertisement, a quantity of individual prioritized video frames of the video advertisement to render based upon a selected accelerated frame rate is determined. Accelerated frame rate rendering priority values assigned to the individual prioritized video frames of the video advertisement are identified. Based upon differences among the identified accelerated frame rate rendering priority values assigned to the individual prioritized video frames, a prioritized video frame subset of the individual prioritized video frames is determined. The prioritized video frame subset of the individual prioritized video frames is equal in number to the determined quantity of individual prioritized video frames of the video advertisement and is determined to yield a maximized cumulative set of the identified accelerated frame rate rendering priority values.